Small-signal equivalent circuits

4 Small-signal equivalent circuits

4.1 Introduction

Many electronic systems require voltage gain, current gain or in general power gain. Note that voltage gain or current gain larger than unity can easily and linearly be achieved using passive components such as capacitors and inductors or with transformers. However, if power gain larger than one is required then components that can be used to achieve that power gain larger than 1 must be used. It was already explained in Chapter 1 that this requires non-linear two port devices; in this book we assume BJTs and MOS transistors for this.

In this chapter and in chapter 5, we aim at linear amplifiers³¹ . Linear amplifiers are basic building blocks for many electronic systems. Non-linear amplifiers are also widely applied in e.g. digital circuitry, mixers that serve to shift signals in the frequency domain and in circuits that do analog-to-digital conversions, but these are usually extensions of linear(ized) amplifiers, and are not addressed in this book.

4.2 Linear model for transistors

Using the nonlinear element equations of MOS transistors or BJTs in analyses typically creates cumbersome calculations, and at best yields huge equations that offer very limited insight. Only for relatively simple circuits, closed form expressions that relate e.g. output voltage to input voltage can be derived. One example of this is given below.

pict — Figure 4.1: Example of voltages and collector current in and around an actual amplifier circuit, as a response to a small sinusoidal $v_{IN} (t)$ . Note that $i_{C} (t)$ and $v_{OUT} (t)$ are not sinusoidal. It is assumed that in its operating point, $V_{OUT} = 0$ .

In Figure 4.1, the circuit schematic is shown in the lower right hand side corner. The input signal $v_{in} (t)$ and the voltage-shifted $v_{BE} (t)$ are shown as a function of time in the lower left hand side graph. Note that this plot is rotated $9 0^{\circ}$ to be able to (below) construct $i_{C} (t)$ and $v_{OUT} (t)$ graphically. The resulting $i_{C} (t)$ can be constructed graphically by mirroring the $v_{BE} (t)$ signal in the $i_{C} (v_{BE})$ curve. The voltage at the collector $v_{C} (t)$ and the (DC-free) $v_{OUT} (t)$ then follow by applying Ohm’s law; these are shown in the rightmost graph.

For this quite simple circuit, the voltage $v_{C} (t)$ at the collector node, due to the sinusoidal $v_{in} (t)$ can be derived mathematically. Note that the output voltage $v_{out} (t)$ has the same shape as $v_{C} (t)$ if this circuit is unloaded, but that it may be DC-shifted due to the presence of $C_{out}$ .

\begin{array}{rcl} v_{C} (t) & = V_{CC} - R_{C} \cdot I_{C 0} \cdot (e^{\frac{q \cdot (V_{BE} + V \cdot \sin (ωt))}{kT}} - 1) & (4.1) \end{array}

For more complex circuits, deriving the exact relation between an input signal and an output signal gets quite complicated, resulting in useless relations (in the sense that they do not give any comprehensible insight). From a fundamental point of view, properties such as input impedance, output impedance and circuit bandwidth cannot be derived or defined as these hold for linear(ized) circuits.

Aiming at linear circuits, typically all kinds of linear properties of a circuit are of interest. These include the aforementioned transfer functions, input and output impedances, bandwidths, and more. Being properties of linear circuits, at least many of these are defined in the frequency domain and in impedances. This requires to analyze the linear part of the behavior of a circuit of interest and to regard any deviation from linear behavior as non-ideal.³² . Getting the linear-only part of (4.1) can be done in multiple ways:

1.: derive a non-linear property or transfer for the non-linear circuit and subsequently get the linear part of the circuit behavior from applying a Taylor series expansion. This requires complex non-linear derivations for e.g. $v_{OUT} (v_{IN})$ or $v_{IN} ∕ i_{IN}$ and required typically quite complex series expansion of these equations. In this series expansion, the linear term(s) describe the linearized behavior.
2.: using a first order approximation (from e.g. a Taylor series expansion) of the behavior of each non-linear component, as model for their electrical behavior and using that in subsequent analyses. Note that with this upfront linearization approach, linear analyses can be done, that frequency domain analyses can be done and that hence impedances can be used in analyses.

Note that both approaches of using linearising gives us:

a reasonable (linear) approximation of the behavior of the nonlinear component or circuit around some bias point,
a limited validity of the results. It follows directly from series expansions that the accuracy of the linear approximation decreases with increasing signal excursions about the bias point and decreases with less-linear element equations.

whereas the upfront linearization approach gives us:

a linear circuit that can be easily analyzed,
equations that can be interpreted (hence relations),
insight.

From this is may be clear that the preferred way to analyze linear(ized) behavior of circuits is to apply upfront linearization. after which any linear analysis method in time domain or in frequency domain can be used.

The circuit we obtain after replacing all nonlinear components by their linear approximation using a Taylor series expansion is called the “linear equivalent circuit”. Note that the linear equivalent circuit that contains many DC sources ( $0^{th}$ order Taylor terms) and many linear impedances and many linear controlled sources ( $1^{st}$ order Taylor terms). For the circuit in Figure 4.2(a) and the replacement of the BJT by its linear equivalent in Figure 4.2(c) yields the linear equivalent circuit in Figure 4.2(b).

In the linear equivalent of the BJT, the full first order series expansion of the BJT is used. This includes DC-voltages, DC-currents and the four partial derivatives of the two port currents to the two port voltages. The DC sources in this equivalent circuit are only relevant for the DC levels of currents and voltages of the circuit and are hence irrelevant for signal properties³³ .

4.3 Small signal equivalent models for transistors and circuits

In the circuit on the left hand side of Figure 4.2, the BJT is replaced by a $1^{st}$ order Taylor expansion to get the linear equivalent circuit on the right hand side. In that linear equivalent, the DC contributions are irrelevant for derivation of signal transfer, input impedances, output impedances, ... and can be freely omitted³⁴ . To analyze (or synthesize) the behavior of circuits for signals, it can be concluded that only the first order Taylor series expansion terms are of interest. Higher order terms and zero-th order terms are then irrelevant.

The equivalent of a non-linear component or non-linear circuit that only includes the first order series expansion terms is called a small signal equivalent circuit. For the circuit in Figure 4.3(a), the BJT should then be replaced as shown in Figure 4.3(b).

In the small signal equivalent shown in Figure 4.3(c), also the first order-only expansion terms for the other components are used.

For the resistors and capacitors, the first-order only equivalent equals their resistance respectively capacitance.. Independent signal sources that actually provide a signal are kept in.

Independent DC-sources do not provide any signal: they provide a DC level of voltage or current. In the circuit in Figure 4.3(c) these DC sources are replaced by their impedance at signal frequencies. DC-voltage sources then translate into a short ( $∂v ∕ ∂i = 0 Ω$ ) while DC-current sources translate into an open ( $∂i ∕ ∂v = 0 S$ ). The small signal equivalent circuit hence does not include any DC-source.

4.4 SSEC of a BJT

A small-signal equivalent circuit of a BJT follows from the most general expression for the base current $i_{B}$ and collector current $i_{C}$ of a BJT. Shown below is the derivation for NPNs.

The element equations for an NPN are shown in (4.2) and (4.3). The rightmost term in (4.2) models an unwanted dependency of $I_{C}$ on $v_{CE}$ , using the so-called Early-voltage $V_{A}$ .

\begin{array}{rcl} i_{C} & = I_{C 0} (e^{\frac{q v_{BE}}{kT}} - 1) \cdot (1 - e^{\frac{- q v_{CE}}{kT}}) \cdot (1 + \frac{v_{CE}}{V_{A}}) & (4.2) \\ i_{B} & = \frac{1}{α_{fe}} \cdot i_{C} & (4.3) \end{array}

Note that the NPN is usually operated with $V_{CE} > 0.1 V$ where the second term between brackets is close to one and hence can be neglected. Figure 4.4 shows actually 4 graphs to capture the most relevant i-v relations of an NPN in a specific operating point in one figure. For readability the numbers on the axes (and the units) are omitted and the $i_{B}$ axis and $i_{C}$ axes are scaled differently for the same reason.

$i_{C} (v_{CE})$ is shown in the first quadrant, for the $V_{BE}$ in the operating point.
Note that the x-axis represents $v_{CE}$ whereas the y-axis corresponds to $i_{C}$ .
$i_{C} (v_{BE})$ for the $V_{CE}$ in the operating point is shown in the second quadrant.
For this quadrant, the x-axis to the left corresponds to $v_{BE}$ .
$i_{B} (v_{BE})$ for the $V_{CE}$ in the operating point is depicted in the $3^{rd}$ quadrant.
The downward y-axis corresponds to $i_{B}$ and is differently scaled as the $i_{C}$ -axis for readability.
$i_{B} (v_{CE})$ for the $V_{BE}$ in the operating point is in the forth quadrant. For this curve, a small dependency of $I_{B}$ on $v_{CE}$ is assumed.

The bias point for this transistor is marked by the (4) dots that correspond to the voltages and current combinations in that bias point: ${I_{C}, V_{CE}}$ , ${I_{C}, V_{BE}}$ , ${I_{B}, V_{BE}}$ , and ${I_{B}, V_{CE}}$ respectively. The lightgray vertical and horizontal lines ’“connect” these 4 points for illustration reasons.

A Taylor expansion for $i_{C}$ and $i_{B}$ about the bias point $i_{C} = I_{C}$ respectively $i_{B} = I_{B}$ then gives:

\begin{array}{rcl} I_{C} + d (i_{C}) & = & i_{C} (V_{BE}, V_{CE}) \\ + \frac{1}{1!} (\frac{\partial i_{C}}{\partial v_{BE}} \cdot (v_{BE} - V_{BE}) + \frac{\partial i_{C}}{\partial v_{CE}} \cdot (v_{CE} - V_{CE})) + . . . \\ I_{B} + d (i_{B}) & = & i_{B} (V_{BE}, V_{CE}) \\ + \frac{1}{1!} (\frac{\partial i_{B}}{\partial v_{BE}} \cdot (v_{BE} - V_{BE}) + \frac{\partial i_{B}}{\partial v_{CE}} \cdot (v_{CE} - V_{CE})) + . . . \end{array}

The zeroth-order terms correspond to the bias point settings, and hence correspond to the dots in Figure 4.4 and in Figure 4.5. The zero-th order terms and the first order terms combined represent “first-order” or linear approximations about the bias point. Figure 4.5 shows the transistor’s i-v-characteristics in gray, the bias point as dots and shows the linear approximation of the i-v-curves about the bias point as thick line segments.

The difference between the actual transistor behavior — the actual non-linear i-v-characteristics — and the linear approximation is small for small (in voltage and current) excursions about the bias point. Mathematically they are described by the sum of all higher order terms in the Taylor series expansion. In so-called small-signal analyses and in small-signal operation of a circuit, it is assumed that the linear approximation is sufficiently accurate.³⁵

For small variations, the terms ( $v_{BE} - V_{BE})$ and ( $v_{CE} - V_{CE}$ ) can be replaced by their differential notations; $d (v_{BE})$ and $d (v_{CE})$ . This can be written even shorter by replacing the differential terms by “small-signal symbols”: for example the base voltage variation $d (v_{BE}) \equiv v_{be}$ and the collector current variation $d (i_{C}) \equiv i_{c}$ . Taking into account only the terms that describe the variations — the first order terms in the expansion — this yields

\begin{array}{rcl} d (i_{C}) \equiv i_{c} = \frac{\partial i_{C}}{\partial v_{BE}} \cdot v_{be} + \frac{\partial i_{C}}{\partial v_{CE}} \cdot v_{ce} & (4.4) \\ d (i_{B}) \equiv i_{b} = \frac{\partial i_{B}}{\partial v_{BE}} \cdot v_{be} + \frac{\partial i_{B}}{\partial v_{CE}} \cdot v_{ce} \end{array}

The small-signal equivalent circuit (SSEC) of an NPN, corresponding to the equations in (4.4), is shown in Figure 4.6.

With the SSEC of an NPN as in Figure 4.6, to construct a SSEC of a circuit, every NPN should be replaced by 2 resistors and 2 voltage controlled current sources. This means that the SSEC contains many more components than the original circuit. The advantage is of course that the SSEC is linear whereas the original circuit was inherently nonlinear. For most applications, using the full SSEC of an NPN is not necessary: some components may be neglected and hence may be left of the SSEC. The next list enumerates the components in descending order of importance:

the controlled output current is THE reason to use a transistor: it may not be left out except if you’re modelling a destroyed transistor. The current variation forced by this source equals $v_{be} \cdot d i_{C} ∕ d v_{BE}$ .
the base current is just as fundamental, but unwanted. The (small-signal) base current as a response to a (small-signal) base-emitter voltage corresponds to the resistor between B and E and can not be omitted.
the output resistance, the resistor between C and E, only is relevant if an external load impedance of the BJT is high ohmic compared to the transistor’s output impedance. Only in that case the transistor’s output resistor must be included, and it can freely — and should to limit calculation complexity — be excluded otherwise.
the input current as a result from output voltage variations is usually small and can usually be neglected.

Hence the SSEC to be used is usually the one shown in Figure 4.7a. Only if the load of the transistor is very high ohmic (such as using a DC current source as load) then the SSEC in Figure 4.7b should be used.

4.4.1 Notational simplification

The notation used in (4.4) and in Figure 4.7 is not that easy to read. For that reason meaningful short hand notations are introduced for some properties of the components in the SSEC of the BJT:

the main use of the BJT is to create an output current variation from its input voltage variation. The ratio between the two is called the transconductance $g_{m}$ :

$g_{m} = \frac{\partial i_{C}}{\partial v_{BE}} \equiv \frac{i_{c}}{v_{be}}$ (4.5)
the base current is fundamental, and is a factor “current gain” or $cgain$ smaller than the output current. Consequently the corresponding resistor between B and E has a value:

$r_{be} = {(\frac{\partial i_{C}}{α_{fe} \cdot \partial v_{BE}})}^{- 1} = \frac{α_{fe}}{g_{m}}$ (4.6)
in many applications, achieving a high voltage gain is very important. It can be derived that the maximum achievable voltage gain factor using passive load impedances equals the product of the $g_{m}$ and the transistor’s output resistance $r_{ce}$ ; for this product the symbol $μ$ is frequently used, leading to:

$r_{ce} \equiv \frac{μ}{g_{m}}$ (4.7)

Using these short hand notations, the resulting SSEC for a BJT is shown below. As stated before, the most simple version that can be used, should be used. This usually means that the SSEC of choice consists of only 2 linear components: the voltage controlled current source that represents the essence of the transistor and the input resistor that represents the fundamentally present main unwanted effect: input current.

4.4.2 Small signal equivalent of PNPs

Note that the above derivations of small signal equivalents was done for NPN transistors. For the PNPs the derivation is very similar. To recap, the element equation of PNP are the same as those for an NPN — listed in (4.8) and (4.9) — except for the sign of the terminal currents and the sign of the port voltages:

\begin{array}{rcl} i_{C} & = I_{C 0} (e^{\frac{- q v_{BE}}{kT}} - 1) \cdot (1 - e^{\frac{q v_{CE}}{kT}}) \cdot (1 + \frac{v_{CE}}{V_{A}}) & (4.8) \\ i_{B} & = \frac{1}{α_{fe}} \cdot i_{C} & (4.9) \end{array}

Note that whereas $I_{C 0} > 0$ for NPNs, for PNPs $I_{C 0} < 0$ . Likewise, the early voltage $V_{A}$ is positive for an NPN and negative for a PNP.

Having the exact same element equations but with current signs and voltage signs opposite from those for NPNs, the derivatives $\partial i_{x} ∕ \partial v_{y}$ are the same for NPNs and PNPs. The small signal equivalent of a PNP is hence identical to that of an NPN, and hence is also depicted in Figure 4.8.

4.5 SSEC of a MOS transistor

The previous section described the (linear) small-signal equivalent circuit for a BJT; the work in that section is repeated here to get the SSEC for a MOS transistor. Starting with the element equations of an NMOS transistor (the drain current equations are for strong inversion saturation and strong inversion linear region respectively):

\begin{array}{rcl} i_{G} = i_{G} (v_{GS}, v_{DS}) = 0 \\ i_{D, saturation} = i_{D} (v_{GS}, v_{DS}) = \frac{1}{2} K \cdot {(v_{GS} - V_{T})}^{2} (1 + λ v_{DS}) & (4.10) \\ i_{D, linear} = i_{D} (v_{GS}, v_{DS}) = K \cdot ((v_{GS} - V_{T}) \cdot v_{DS} - \frac{1}{2} v_{DS}^{2}) \end{array}

In the expression for the saturation region, the term $(1 + λ v_{DS})$ models the unwanted dependency of $I_{D}$ on $v_{DS}$ via $λ$ ; this term is only relevant if the external load impedance of the MOS transistor is high ohmic compared to the transistor’s output impedance. In all other cases we can freely neglect this term.³⁶ . Similar to what was done in $4.4, Figure 4.9 shows 2 graphs to capture the most relevant (DC) i-v relations of a MOS transistor in a specific operating point in one figure.:

$i_{D} (v_{DS})$ for the $V_{GS}$ in the operating point; this curve is shown in the first quadrant.
$i_{D} (v_{GS})$ for the $V_{DS}$ in the operating point; this curve is shown in the second quadrant.

The bias point for this transistor is marked by the (2) dots that correspond to the voltages and current combinations in that bias point: ${I_{D}, V_{DS}}$ and ${I_{D}, V_{GS}}$ respectively. The light-gray horizontal lines ’“connect” these two points for illustration reasons.

The SSEC for the MOS transistor now follows from a first-order Taylor series expansion:

\begin{array}{rcl} d (i_{G}) = i_{g} = \frac{\partial i_{G}}{\partial v_{GS}} \cdot v_{gs} + \frac{\partial i_{G}}{\partial v_{DS}} \cdot v_{ds} \\ d (i_{D}) = i_{d} = \frac{\partial i_{D}}{\partial v_{GS}} \cdot v_{gs} + \frac{\partial i_{D}}{\partial v_{DS}} \cdot v_{ds} & (4.11) \end{array}

The zeroth-order series expansion terms are the bias point settings, and correspond to the dots in Figure 4.9. The zero-th order and the first order terms together form a linear approximations about the bias point. Figure 4.10 shows the transistor’s i-v-characteristics in gray, the bias point as dots and shows the linear approximation of the i-v-curves about the bias point as thick line segments.

Just like BJTs and vacuum tubes, a MOS transistor behaves essentially a voltage controlled current source. The parameter $\frac{\partial i_{D}}{\partial v_{GS}}$ is the most important small-signal parameter; just like for the BJT this parameter is called transconductance $g_{m}$ . The parameter $\frac{\partial i_{D}}{\partial v_{DS}}$ corresponds to the output conductance and is denoted with the symbol $g_{ds}$ ; this output conductance can also be written as an output resistance $r_{ds} = 1 ∕ g_{ds}$ . For small-signals (variations) in drain current:

i_{d} = g_{m} \cdot v_{gs} + g_{ds} \cdot v_{ds}

(4.12)

where in saturation

\begin{array}{rcl} g_{m} = K (v_{GS} - V_{T}) \cdot (1 + λ \cdot v_{DS}) \\ g_{ds} \equiv \frac{g_{m}}{μ} = \frac{1}{2} K {(v_{GS} - V_{T})}^{2} \cdot λ & (4.13) \end{array}

These SSEC parameters are specific for the bias point for the transistor: the SSEC parameters follow from a Taylor series approximation about the bias point. Because of this, in the equations above, $v_{GS} = V_{GS}$ and $v_{DS} = V_{DS}$ . The resulting small-signal equivalent circuit of an NMOS transistor is shown on the left hand side in figure below. The effect of the output resistance is often neglected; in this case the SSEC for an NMOS transistor can be simplified to that on the right hand side in the figure. Similar to the situation for NPNs and PNPs, the small signal equivalent circuit of a PMOS transistor is equal to that of an NMOS transistor.

4.6 Small-signal parameters

For calculations using the SSEC of a BJT or MOS transistor, the various small-signal parameters (mainly the $g_{m}$ , the $r_{be}$ and only the $r_{ce}$ or $r_{ds}$ when required) must be known. These small-signal parameters follow from the bias point and the element equations.

4.6.1 BJT

The most important small-signal parameter of the BJT is the change in collector current $i_{C}$ due to a change in the base-emitter voltage $v_{BE}$ : represented by the transconductance $g_{m}$ . From its definition $g_{m} = \frac{\partial i_{C}}{\partial v_{BE}}$ and the element equation for an NPN transistor we get:

\begin{array}{rcl} g_{m} & = \frac{q}{kT} \cdot I_{C 0} \cdot e^{\frac{q \cdot v_{BE}}{kT}} \cdot (1 + \frac{v_{CE}}{V_{A}}) \\ g_{m} & = \frac{q}{kT} \cdot I_{C 0} \cdot e^{\frac{q \cdot v_{BE}}{kT}} \\ ≅ \frac{q}{kT} I_{C} & (4.14) \end{array}

where the first small signal element equation includes a (small) dependency on $V_{CE}$ . For the PNP the same equations result. Whenever possible the second — simplified — small signal element equation will be used. It can be seen that the transconductance of a BJT is proportional to its DC (bias) current $I_{C}$ . For the $r_{be}$ :

\begin{array}{rcl} r_{be} & \equiv {(\frac{i_{b}}{v_{be}})}^{- 1} = \frac{α_{fe}}{I_{C 0} \cdot e^{\frac{q \cdot v_{BE}}{kT}} \cdot \frac{q}{kT}} \\ = \frac{α_{fe}}{g_{m}} & (4.15) \end{array}

The output resistance of a BJT — $r_{ce} = I_{C} ∕ V_{A}$ — follows from the element equations and the bias conditions as well. However in this book we use either a prespecified $r_{ce}$ or a value related to a prespecified maximum achievable gain: $r_{ce} = μ ∕ g_{m}$ .

4.6.2 MOS transistor

For the MOS transistor, similar quite simple relations can be derived for the small-signal parameters. From the element equations for an NMOS transistor, for operation in strong inversion and saturation (for now the linear region is neglected):

\begin{array}{rcl} i_{D} = \frac{1}{2} \cdot K \cdot {(v_{GS} - V_{T})}^{2} \cdot (1 + λ v_{DS}) & (4.16) \\ i_{G} = 0 \end{array}

The most essential parameter — the transconductance — can be calculated to be $g_{m} = K \cdot (v_{GS} - V_{T}) \cdot (1 + λ v_{DS})$ . The last term in this expression is preferably neglected, yielding $g_{m} = K \cdot (v_{GS} - V_{T})$ . This $g_{m}$ follows from the $V_{GS}$ in the bias point (and $V_{DS}$ in the bias point if we have to include a finite output resistance) and from the transistor property $K$ . Reusing the transistor’s element equation, this equation for $g_{m}$ can be rewritten into 3 useful forms that can be used to calculate the transconductance:

\begin{array}{rcl} g_{m} & = \sqrt{2 K \cdot I_{D} \cdot (1 + λ \cdot V_{DS})} \\ ≅ \sqrt{2 K I_{D}} & (4.17) \\ = K \cdot (V_{GS} - V_{T}) \\ = \frac{2 I_{D}}{V_{GS} - V_{T}} \end{array}

Which of these equations is most useful depends entirely on which properties are known; usually 2 out of the 3 possible parameters ${K, V_{GS}, I_{D}}$ are known and can be substituted in one of the 3 $g_{m}$ -equations. The equations for PMOS transistors are identical.

Charge storage in transistors: small signal capacitances

As explained in chapter 2, there is charge storage in every junction that is non-linearly dependent on the voltage drop across the junction. Small signal wise, this translates into having to associate a small signal capacitance with every junction.

For BJTs this corresponds to 2 small signal capacitances, one associated with the B-E-junction and one associated with the B-C-junction. As explained in chapter 2 these capacitances are bias point dependent. A more accurate small signal equivalent model for BJTs, then the ones introduced earlier in this chapter — still neglecting the $\partial i_{B} ∕ \partial v_{CE}$ term — is then

pict

For MOS transistors, in this book it is assumed that the source and bulk are tied together, see e.g. $2.5. As a result, only one junction — the drain-bulk-junction — is present in the MOS transistors in this book. Apart from that, MOS transistors fundamentally operate by creating/modulating an inversion layer between source and drain, using the gate (voltage). This translates into charge storage associated with both the gate-source voltage and associated with the gate-drain voltage. Small signal wise, this may be modelled as a gate-source capacitance and a gate-drain capacitance., both being bias-dependent. A more accurate small signal equivalent model for MOS transistors than the ones introduced earlier is then

pict

No in-depth analyses nor descriptions concerning these capacitances will be given in this book - that is considered outside the scope of this book.

Elaborate small signal models for transistors

Elaborate small signal modes — are used for e.g. very accurate calculations and for simulations — include many more small signal components. These models follow from equations describing the node currents as function of all node voltages and from the equations that describe charge storage in transistors by charge assigned to each node, as a function of all node voltages.

For a BJT these equations are then, very much simplified:

\begin{array}{rcl} i_{C} = f_{IC} (v_{C}, v_{B}, v_{E}) \\ i_{B} = f_{IB} (v_{C}, v_{B}, v_{E}) \\ i_{E} = f_{IC} (v_{C}, v_{B}, v_{E}) \\ Q_{C} = f_{IC} (v_{C}, v_{B}, v_{E}) \\ Q_{B} = f_{IB} (v_{C}, v_{B}, v_{E}) \\ Q_{E} = f_{IE} (v_{C}, v_{B}, v_{E}) \end{array}

which leads to

$3 \cdot 3 = 9$ (trans)conductances $g_{xy} = \frac{\partial i_{X}}{\partial v_{Y}}$ and to
$3 \cdot 3 = 9$ (trans)capacitances $c_{xy} = \frac{\partial Q_{X}}{\partial v_{Y}}$ .

Note that e.g. a transcapacitance $c_{gd}$ in general is not equal to $c_{dg}$ : the change in (here) gate charge $Q_{G}$ due to a drain voltage change can be completely different from the change in drain charge $Q_{D}$ due to a gate voltage change. The same holds of course for transconductances $g_{xy}$ and $g_{yx}$ for all $x \neq y$ : they are not identical. In the small signal models that are suitable for hand derivations, quite significant simplification are introduced leading to the models presented earlier in this chapter.

One of the 3 node voltages can be seen (or denoted) as a reference voltage, which results in quite some redundancy in the $9$ (trans)conductances and $9$ (trans)capacitances. It can readily be seen that deriving the $c_{xy}$ and $g_{xy}$ for 2 nodes, regarding the other node as reference is sufficient to describe all small signal properties. Hence the full set of $9$ transcapacitances and $9$ transconductances can also be uniquely described by $2 \cdot 2 = 4$ transcapacitances and $2 \cdot 2 = 4$ transconductances.

For a MOS transistor, in this book a 3-terminal device is assumed for simplicity reasons: the bulk and source terminals are assumed to be shorted. In a more general notion this is not the case and the node current and node charge can be defined for all 4 nodes. In a way that is similar to that for BJTs this leads to

$4 \cdot 4 = 16$ (trans)conductances $g_{xy} = \frac{\partial i_{X}}{\partial v_{Y}}$ and to
$4 \cdot 4 = 16$ (trans)capacitances $c_{xy} = \frac{\partial Q_{X}}{\partial v_{Y}}$ .

where $x, y \in {D, G, S, B}$ . Again, there is quite some redundancy in these transcapacitances and transconductances. Using one of the nodes as reference (usually the bulk or source is used for that), $9$ unique transcapacitances and $9$ unique transconductances follow that are sufficient to describe all $2 \cdot 16$ small signal parameters.

4.7 Amplifier circuits

It was demonstrated in chapter 3 that a transistor needs proper biasing — in some DC bias point — to be able to perform. The current chapter deals with small input signal variations about the bias point to get some output current variations that can — using Ohm’s Law — be transformed into output voltage variations. It is hence crucial that transistors in a specific circuit are both properly biased at a DC level, that AC input signals can be applied to the transistors and that the resulting AC output signal can be used in some way.

4.7.1 Coupling the input and output

In a real circuit applying variations onto the input of a transistor can be done in multiple ways:

the most easy way may seem driving a transistor with a series connected DC voltage source and AC signal source. However, putting two voltage sources in series proves to be hard in actual circuitry.
something else

One of the most straightforward ways of that “something else” is used throughout this book. Noting that the bias voltage is fundamentally DC and a signal is fundamentally AC opens possibilities to add voltages. This is worked out using a circuit in Figure 3.5b, now used to amplify an input voltage $v_{i} (t)$ :

Coupling the AC voltage source directly between B and E would prevent (independent of the input signal) realising a suitable bias point for the transistor: replacing the “?” by a short will not work out nicely. Elaborating a little leads to a number of requirements for coupling the input signal $v_{i} (t)$ to the input terminals of the transistor:

coupling the input signal may not disrupt the DC bias of the transistor
the input signal must, preferably, not be attenuated by the coupling

This seems to be a contradiction: on one hand, the input signal should be coupled onto the transistors’ input terminals, while on the other hand it shouldn’t. The solution is to satisfy both requirements at the same time, but not for the same frequency. We can now redefine the requirements:

for DC, the coupling component must have a high impedance in order not to disturb or compromise proper (DC) biasing settings
for signal frequencies, the coupling component must have a low impedance

Again, there are multiple solutions to this problem. Firstly, an inductive bias circuit can be used in combination with a signal source that has a non-zero series resistance. This type of solution is mainly used in circuits operating at very high frequencies. Firstly, a coupling component that is high ohmic for $f = 0 Hz$ and that is low ohmic for signal frequencies can be used. This can be accomplished by a capacitor as coupling component. The capacitive coupling is used almost exclusively in this book.

With capacitive coupling, the value of the capacitor is not relevant for blocking of the DC current: the impedance of any capacitor is infinite for DC signals. For passing the AC voltage from the source to the amplifier, the value of the capacitor is most definitely of importance as it forms — together with the input resistance of the circuit — a first-order high-pass characteristic. If the -3dB corner frequency of that characteristic is sufficiently below the lowest signal frequency the coupling can be considered good for any signal frequency³⁷ .

Example For an amplifier with an input resistance of $r_{in}$ =1 k $Ω$ and an input signal frequency range from 20 Hz to 20 MHz:

if the attenuation due to the coupling has to be smaller than 3 dB, a minimum value for the coupling capacitor $C_{couple}$ follows the signal transfer function:
$\begin{array}{rcl} H (jω) & = \frac{v_{in}}{v_{source}} \\ = \frac{jω \cdot r_{in} C_{couple}}{1 + jω \cdot r_{in} C_{couple}} \end{array}$
Being in a standard form for a first order high pass function (see section 0.14), it directly follows that $ω_{0} = 1 ∕ (r_{in} C_{couple})$ and hence
$\begin{array}{rcl} C_{couple} & \geq \frac{1}{2 π \cdot f_{minimum} \cdot r_{in}} = 8 μF \end{array}$
if the amplifier has to settle within 1% of its bias within 1s after switching on source, the maximum value for the coupling capacitor is:
$\begin{array}{rcl} v_{C} (t) & = v_{C} (t = \infty) \cdot (1 - e^{\frac{- t}{r_{in} C_{couple}}}) \\ \frac{v_{C} (t)}{v_{C} (t = \infty)} & \geq 0.99 \Rightarrow \\ C_{couple} & \leq \frac{t}{r_{in} \cdot \ln (100)} = 220 μF \end{array}$

At the output of the amplifier, there is a similar coupling issue. The voltage at the collector of the transistor is the sum of the DC bias voltage and of the desired AC output voltage. To pass only the signal to the load or to a subsequent circuit, a coupling circuit or component should be used. Also here, a capacitor may do just fine for this purpose.

4.8 SSEC of a basic amplifier circuit

To calculate small-signal properties of circuits — such as input impedance, output impedance, bandwidth or signal gain —first we need an SSEC of the total circuit. Whereas the circuit itself comprises transistors, sources, passive components and more, its small signal equivalent circuit is the first order only representation of the original circuit. This (linear) SSEC then can be analyzed using all the theorems, rules, tips and tricks of linear network analysis.

As example, after creating an SSEC for the circuit in Figure 4.12, a few derivations of small-signal parameters are shown. Figure 4.13 shows a step-by-step derivation of an SSEC.

In the first step components are replaced by their small signal equivalents. For this particular circuit, the BJT is replaced by its SSEC and DC sources are set to 0. When replacing non-linear components by their SSEC it is very important to keep track of the original position of (here) the base, collector and emitter terminals.

The second step is redrawing and simplifying the SSEC obtained after the first step: this usually boils down to plain redrawing and redrawing... To reduce complexity in this step, parallel impedances may be merged into single equivalent impedance. The SSEC in Figure 4.13c is a small-signal equivalent of the circuit in Figure 4.13a that can be used to calculate any small signal property of the original circuit. In this example these properties are frequency-dependent gain, input impedance and output impedance.

Usually it is implicitly assumed that coupling capacitances are sufficiently low ohmic at signal frequencies. In this context “sufficiently low ohmic” means that at signal frequencies the voltage drop across the capacitors is negligibly small and hence the capacitors can then be modelled as shorts. In that case the SSEC in Figure 4.13c can be simplified to the SSEC in Figure 4.13d.

Using the SSEC in Figure 4.13d, now a few small-signal properties will be derived for the circuit in Figure 4.13a:

input impedance
The input impedance of an amplifier is the impedance we “see” looking from the controlling source “into” the input port of the circuit. According to Ohm’s law $z_{in} = v_{in} ∕ i_{in}$ , or for a purely resistive input impedance $r_{in} = v_{in} ∕ i_{in}$ . Deriving $z_{in}$ can be done in many ways, relatively easy ones being driving the input of the circuit with a small signal voltage source $v_{in}$ and calculating the resulting $i_{in}$ or driving $i_{in}$ and calculating $v_{in}$ . The ratio of the two yields $z_{in}$ .

For the SSEC in Figure 4.13d and hence for the circuit in Figure 4.14 this yields $r_{in} = α_{fe} ∕ g_{m} ∕ ∕ R_{B}$ .

Figure 4.14: Amplifier circuit with BJT and SSEC to derive the input impedance
output impedance
The output impedance of the amplifier is the impedance “seen” when looking “into” the output port of the circuit. Similar to the derivation of input impedance, output impedance is $z_{out} = v_{out} ∕ i_{out}$ when driving the output port by either a voltage source $v_{out}$ or by a current source $i_{out}$ . Note that any other signal source should be set to 0 in this case. Another method that does not require introducing an output port driving source, but that requires an input signal source, is loading the output of the amplifier by two different impedances deriving $z_{out}$ from he resulting output voltages and/or output currents. In the limit case an infinite load impedance (an open) and a zero load impedance (a short) may be used, leading to $z_{out} = v_{out, open} ∕ i_{out, short - circuit}$ .

In this book usually the output port is driven by a signal source, having all other independent signal set to zero, and calculating $z_{out} = v_{out} ∕ i_{out}$ . An example of this is given in Figure 4.15, yielding $r_{out} = R_{C}$ .

Figure 4.15: Amplifier circuit with BJT and SSEC to derive the output impedance
voltage gain:
The voltage gain (i.e. voltage amplification factor) of the amplifier can readily be evaluated — from Figure 4.14 — to be $A_{v} \equiv v_{out} ∕ v_{in} = - g_{m} \cdot R_{C}$ .

To derive small signal properties of circuits including other types of non-linear components, such as MOS transistors, the same approach can be applied. The MOS equivalent of the amplifier in Figure 4.14 and its SSEC are shown in Figure 4.16.

Using the SSEC, we can readily derive that the input impedance is $R_{G 1} ∕ ∕ R_{G 2}$ , that the voltage gain equals $A_{v} = - g_{m} \cdot R_{D}$ and that (using a little modified SSEC — driving the output port and setting all other independent sources to 0) the output impedance is equal to $R_{D}$ .

4.8.1 Design procedure - an example

We want to design an amplifier with a BJT that has a voltage gain of $| A_{v} | = 100$ . Note that the basic amplifier circuit of Figure 4.13a is an inverting amplifier for which $A_{v} = - g_{m} \cdot R_{C}$ . Usually it is not relevant whether an amplifier is inverting or not, as long as we’re only interested in voltage gain. Then we can use $| A_{u} | = g_{m} \cdot R_{C}$ which directly leads to requiring $g_{m} \cdot R_{C}$ =100. Using

\begin{array}{rcl} g_{m} ≅ \frac{q}{kT} I_{C} \\ | A_{v} | ≅ \frac{q}{kT} I_{C} R_{C} \end{array}

where $I_{C}$ is the collector bias current level, it follows that the voltage drop across $R_{C}$ equals $V_{RC} = I_{C} R_{C} = | A_{v} | \cdot kT ∕ q$ which amounts to 2.58V at room temperature. Ignoring non-linear effects — hence assuming sufficiently proper small signal behavior — the supply voltage needs to be high enough to support

$V_{RC} = I_{C} \cdot R_{C}$ ,
a minimum $V_{CE, \min} \approx 100 mV$ to keep the BJT in active forward operation
a voltage amplitude at the collector node $| A_{v} | \cdot V_{in}$ .

Note that when assuming a linearized equivalent of the amplifier, the input signal magnitude $V_{in} \leq \frac{kT}{q}$ to keep the linearized collector current positive and to keep the collector voltage positive. The minimum supply voltage for our CEC amplifier then equals

\begin{array}{rcl} V_{CC} \geq | A_{v} | \cdot \frac{kT}{q} + | A_{v} | \cdot V_{in} + 0.1 V (V_{in} \leq \frac{kT}{q}) \end{array}

For $V_{in} \approx \frac{kT}{q}$ the collector current changes quite a lot: by up to a factor $e$ larger or $e^{- 1}$ smaller than the bias current $I_{C}$ which implies that the operation of the BJT is not small signal and therefore may not be sufficient linear. To get sufficiently linear behavior of this amplifier, the input signal must be sufficiently small to ensure that the variation in collector current ( $i_{c}$ ) is much smaller than the DC bias collector current $I_{C}$ . For this circuit, this can be translated in accepting only input signal voltage levels up to a few mV (depending on linearity or distortion demands).

The graphs below show the BJT’s collector voltage $v_{C} (t)$ and the linearized $v_{C, lin} (t)$ for a CEC designed for $| A_{v} | = 100$ , $v_{in} (t) = V_{in} \cdot \sin (2 π 1000 \cdot t)$ , maximum $V_{in} = \frac{kT}{q}$ using the corresponding minimum $V_{CC}$ , $R_{C} = 2.58 k Ω$ and $I_{C} = 1 mA$ . In the graph on the left $V_{in} = \frac{kT}{q}$ , while in the graph on the right $V_{in} = \frac{kT}{q} ∕ 4$ .

If the input signal amplitude $V_{in}$ is known to be smaller than $\frac{kT}{q}$ , the minimum required supply voltage can be lowered with respect to the situation in the previous two graphs. Assuming a maximum $V_{in, \max} = \frac{kT}{q} ∕ 4$ and adjusting the supply voltage to the corresponding minimum $V_{CC} = I_{C} R_{C} + g_{m} R_{C} V_{in, \max} + 0.1$ :

Using more complex circuit topologies, the gain-supply voltage trade off can be circumvented: then high gain at low supply voltage can be obtained. For this, typically multiple amplifier stages are cascaded. Also the requirement that the input voltage be restricted to several mV to get sufficiently linear behavior can be circumvented. This is usually at the cost of extra components, and requires feedback which in turn usually comes at the cost of power consumption and a lower maximum frequency of operation. These are topics of upcoming chapters in this book.

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