5 Amplifier circuits

5.1 Basic amplifier circuits

In chapter 4, two simple amplifier circuits were analyzed using small signal equivalent circuits. Figure 4.13 showed a very basic amplifier with one BJT (and its SSEC). In that circuit, the transistor is driven at the $B-E$ port while the output port is between $C$ and $E$. This may be somewhat hard to see in the original circuit, but for sure it is very visible in its SSEC. The MOS version is shown in Figure 4.16, in which the transistor is driven at the $G-S$ port and where the output port includes the $D$ and the $S$ terminals. These circuits are both repeated in Figure 5.1

In general a transistor is a three terminal device that behaves like a (nonlinear) voltage controlled current source (VCCS). To be able to behave like a VCCS a device must be at least a two-port device. From a fundamental point of view a two-port device has 4 terminals, whereas a transistor has just 3 which implies that the two ports share one terminal.

For a circuit using a BJT this yields 3 ways to share terminals between input and output port:

• a common-emitter circuit (CEC) in which the emitter is shared by the input port and output port. Due to the nature of the BJT, the input port must be formed by the $v_{\mathit{be}}$ voltage while the output port voltage is $v_{\mathit{ce}}$. The emitter node is common in the input and output port, hence the name CEC.
• a common-base circuit (CBC) in which the base is shared by the input port and output port. So the input port must be formed by the $v_{\mathit{be}}$ voltage while the output port voltage is $v_{\mathit{cb}}$.
• a common-collector circuit (CCC) in which the collector is shared by the input port and output port. Therefore for this case, the input port must be formed by $v_{\mathit{bc}}$ while the output port voltage is $v_{\mathit{ec}}$.

All these basic circuits using one BJT have distinct small-signal properties. The figure below lists the 3 possible configurations³⁸ , starting from the generalized bias circuit for a BJT:

The generalized bias circuit for one BJT is shown in Figure 5.2a. In all circuits either the base or the emitter or both are directly driven by the input signal; driving is done via (DC blocking) capacitances. Drawing one voltage mesh including the input signal and one transistor node pair and drawing one voltage mesh that includes both the output port of the circuit and one transistor node pair directly reveals the common node (in both meshes). In this way Figure 5.2b represents the common-collector circuit (CCC), while Figure 5.2c is the common-emitter circuit (CEC) and Figure 5.2d is the common base circuit (CBC).

Equivalently, for basic amplifier circuits using a MOS transistor this yields:

• a common-source circuit (CSC) in which the source is shared by the input port and output port. Due to the nature of the MOS transistor, the input port must be formed by the $v_{\mathit{gs}}$ voltage while the output port voltage is $v_{\mathit{ds}}$.
• a common-gate circuit (CGC) in which the gate is shared by the input port and output port. Hence the input port is formed by the $v_{\mathit{gs}}$ voltage while the output port voltage is $v_{\mathit{dg}}$.
• a common-drain circuit (CDC) in which the drain is shared by the input port and output port. Therefore the input port is formed by $v_{\mathit{gd}}$ while the output port voltage is $v_{\mathit{ds}}$.

These three configurations are shown in figures 5.3c, d and b respectively.

5.1.1 The common-base circuit (CBC)

The CBC is shown again in Figure 5.4a; figure 5.4b gives its small-signal equivalent circuit for frequencies where the impedances $1∕\mathit{j\omega }{C}_1$ and $1∕\mathit{j\omega }{C}_2$ are small enough to be negligible compared to the other impedances. Finally, Figure 5.4c gives a more comprehensible equivalent circuit, obtained by cleaning up the intermediate SSEC as much as possible. This SSEC is now used to calculate some small-signal properties of the CBC: its input and output resistance, as well as the small signal voltage gain.

The small-signal input resistance is, by definition, the quotient of $v_{\mathit{in}}$ and $i_{\mathit{in}}$. Using the brute force method, and using a driving voltage source:

Substituting these equations gives for the input resistance:³⁹

Equation (5.1) shows that the input resistance of a CBC consists of three components. For decent BJTs, the current gain factor ${\alpha }_{\mathit{fe}}$ is quite large, resulting in an ${\alpha }_{\mathit{fe}}∕g_m$ term that is negligible compared to the $1∕g_m$ term. Using the relation for transconductance of a BJT it follows that for the terms $R_E$ and $1∕g_m$:

from which we see both terms are identical in size for a DC bias voltage drop across $R_E$ as low as $\mathit{kT}∕\mathit{q\cong }$25 mV. In pretty much all CBC circuits, this voltage drop is significantly larger — usually at least some tenths of a volt — which gives an input resistance

The small-signal voltage transfer is the ratio of voltage variation at the output due to a variation at the input. Again, using the brute force method:

Note that the input and output voltages are in phase, in contrast to the situation for the CEC where the gain is negative and hence the phase difference is (ideally) $180^{\circ }$.

The small-signal output resistance of a circuit can be obtained in a number of ways. For linear circuits (as the SSEC), the three methods which are used most often are:

Note that in the last two methods the input signal source is set to zero. For an input voltage source this translates in effectively shorting the input node in the SSEQ, while for an input current the input current source is to be replaced by an open. Application of the first method, using equation (5.3) gives:

This method requires 2 calculations, while the output of the amplifier at the other two methods is driven with a current or voltage source yielding the output impedance directly. These latter two methods are mostly used in this book.

5.1.2 The common-gate circuit (CGC)

The MOS equivalent of the CBC is called a common-gate circuit, CGC, and is shown in Figure 5.5. Its input resistance, voltage gain and output resistance will now be derived using Figure 5.5c:

The small-signal input resistance of the circuit can be calculated using e.g. the brute force method. Driving the output with a voltage source and setting the input signal source to zero:

The small-signal voltage gain can be derived the same way as for the CBC: $H=v_{\mathit{out}}∕v_{\mathit{in}}=-g_m\cdot v_{\mathit{gs}}\cdot R_D$ while $v_{\mathit{gs}}=-v_{\mathit{in}}$:

The small-signal output resistance can readily be derived driving the output using e.g. a current source. Note that then all other independent sources are set to zero:

5.1.3 The common-collector circuit (CCC)

The CEC and CBC — and their MOS equivalents CSC and CGC — are circuit configurations in which the transistor is driven between base and emitter for the BJT, and between gate and source for the MOS transistors. This nicely complies with the element equation for the two types of transistors where in the normal operating range of the transistors the output current is a function of the input voltage: $i_C(v_{\mathit{BE}})$ and $i_D(v_{\mathit{GS}})$.

Another useful configuration is the common-collector circuit where the transistor is not directly driven between B and E or between G and S for MOS transistors. Instead, the transistor is driven at the base (gate) while the emitter (source) voltage is set via $i_C$ ($i_D$) and serves as output voltage. The corresponding circuit schematic of the CCC with an NPN is given in Figure 5.6a.

Feedback from output current to the non-driven input node is typically accomplished by a resistor (or impedance) $R_E$. The highest attainable value for $R_E$ is $\infty \mathrm{\Omega }$ using a DC current source instead of $R_E$.

Using a DC current source, it may be clear that the $v_{\mathit{BE}}$ of the transistor is fixed (assuming no external load and hence zero output currents). Then the difference between the input voltage of the CCC and its output voltage is merely a DC shift. The small-signal value of $v_{\mathit{IN}}$ equals that of $v_{\mathit{OUT}}$ and consequently in this case the small-signal gain is exactly one.

In Figure 5.6b, a linear equivalent circuit is shown for frequencies where $1∕\mathit{j\omega }{C}_{\mathit{in}}$ can be neglected. Figure 5.6c gives a more compact version of 5.6b. Here, the name “CCC” speaks for itself: the collector is part of the input and output mesh.

The input resistance Below, the input resistance of the CCC is derived using a driving voltage source. Note that — because of Ohm’s law — we would get a similar expression if we would have used a driving current source. We get:

The equations above are sufficient to calculate everything within this circuit. Since the expression for $v_{\mathit{be}}$ depends on $v_{\mathit{be}}$, we must separate the variables⁴⁰ , yielding:

After simplification of this relation, we may get (5.5). Note that simplification does not change the relation; it merely changes its form, appearance and its readability. The above derivation would have been shorter using a driving current source.

It follows from this relation that the input resistance of the circuit is more or less equal to ${\alpha }_{\mathit{fe}}\cdot R_E$, parallel to the resistance of the input (bias) circuit: the input resistance of a CCC is usually relatively high.

The small signal voltage gain of the circuit equals the ratio between the small signal output voltage and the (driving) input voltage:

From the relation above, it follows that the small signal voltage gain is smaller than or equal to 1. The gain approaches 1 when either the transconductance $g_m$ or the resistance $R_E$ go to infinity. Note that if a current source would have been used instead of $R_E$, the signal transfer (without load impedance) is exactly equal to 1. This circuit is commonly called an “emitter-ollower”⁴¹ , since the output and input voltages have an equal phase and (almost) equal amplitude.

The output resistance In the derivation of the output resistance shown below, it is (arbitrarily) assumed that the output port is driven by a voltage source. In the derivation, all other independent sources must be set to zero (i.e. $v_{\mathit{in}}=0$) yielding:

The dominant factor in the expression for $r_{\mathit{out}}$ is the transconductance of the transistor $1∕g_m$. As numerical example, a bias current of 1 mA yields a small signal output resistance of less than 25 $\mathrm{\Omega }$, which is quite low.

5.1.4 The common-drain circuit (CDC)

The MOS equivalent of the CCC, the CDC, is given in Figure 5.7a. The analysis is analogous to that of the CCC and therefore only the resulting equations are given.

The input resistance From the small signal equivalent circuit in Figure 5.7c it is obvious that (for this simple SSEQ of a MOS transistor) the gate current is 0 A. The input resistance of the CDC is then equal to the parallel impedance of $R_{G1}$ and $R_{G2}$ which yields $r_{\mathit{in}}=R_{G1}∕∕R_{G2}$.

The small signal signal transfer The voltage gain (or transfer) of input to output can be calculated in the same way as for the CCC, resulting in $\frac{v_{\mathit{out}}}{v_{\mathit{in}}}=\frac{g_m\cdot R_S}{1+g_m\cdot R_S}$ which shows that the input signal and output signal are in phase. Analogous to the CCC, this circuit is called a “source-follower”.

The output resistance can easily be obtained from the small-signal equivalent circuit by forcing e.g. a voltage at the output node for $v_g$ = 0:

5.1.5 CEC, CBC, CCC, CSC, CGC and CDC: a comparison

All three variants of the single-BJT amplifier circuits have different small signal properties. Table 1 gives a comparative summary of the results of the three circuits with respect to signal transfer, input and output resistances.

An overview of a number of small signal properties for the three basic MOS circuits is given in Table 2.

5.2 More complex amplifiers

The basic circuits discussed in section 5.1 contain just one transistor. For some applications one of these circuits may do: if the set of small signal properties listed in Table 1 or in Table 2 satisfies all your requirements, you’re done.

However, many times none of the basic circuits in section 5.1 can satisfy a set of small signal requirements for a specific application. For example for an audio power amplifier a requirement may be to design a high $r_{\mathit{in}}$, a low $r_{\mathit{out}}$ and a high voltage gain $|a_v|$. None of the basic circuits in section 5.1 can achieve all these. The basic circuits can however partially satisfy the requirements, see Table 1 and Table 2. The fact that the basic circuits can in general not satisfy an arbitrary set of requirements is a direct consequence of the limited number of degrees of freedom in circuits with just one transistor. If we must satisfy multiple requirements — that are not compatible with any of the basic amplifier circuit — clearly more degrees of freedom must be created. In this chapter this is accomplished by mix-and-match of basic amplifiers into a larger amplifier. In chapter 8 this is extended to opamp-style circuits. As stated, in this section it is mix-and-match.

5.2.1 Mix-and-match

If a specific set of specifications must be met by a circuit — hereby an amplifier — that can only partially be met by any of the basic circuits in section 5.1, a combination of basic circuits just may do the job. For example, if for an amplifier circuit

1.

high input impedance

2.

high voltage gain

3.

low output impedance

is required then — assuming an amplifier with BJTs — the

• CEC can satisfy demand 2, and may be used for requirement 1
• CBC can be used to achieve demand 2
• CCC can satisfy demands 1 and 3.

From this it follows that all demands can be satisfied by cascading basic amplifier stages. Possible implementations that can be designed to meet all requirements include a CEC+CCC cascade (using two stages of amplifiers), and a CCC+CEC+CCC cascade, or a CEC+CBC+CCC cascade, or ... These latter three stage amplifiers can obviously achieve a higher overall voltage gain.

5.2.2 Cascading issues: signal transfer

The next figure shows a linear model of a two-stage amplifier. The amplifier stages are reduced to their bare essence: only the most important parameters are included: the input impedance, output impedance and voltage gain⁴² .

In the representation of a general two-stage amplifier, at both the input and output of each stage a coupling capacitor is included to avoid any possibility for clashing (DC) bias settings. This is however not always required: some basic amplifiers can directly be coupled which may have advantages for bandwidth, power dissipation and (obviously) component count.

In calculating or deriving the overall properties of cascaded amplifiers, both the properties of the amplifiers themselves and the (signal transfer) effect of coupling needs to be taken into account. A few topics related to this are addressed below.

5.2.3 Coupling capacitors: bandwidth limitations

Any coupling capacitor $C$ in combination with a resistive signal source or resistive load introduces a bandwidth limitation for the signal transfer. In the circuit representation in Figure 5.8 this holds for $C_{\mathit{in}}$, $C_{\mathit{couple}}$ and $C_{\mathit{out}}$. The description below assumes signal coupling from $v_g$ via via $C_{\mathit{in}}$ to $v_{\mathit{in}1}$ but is equally valid for the other capacitances.

The voltage signal transfer from $v_g$ to the actual input voltage as experienced by the first stage, $v_{\mathit{in}1}$, is

This signal transfer shows a high-pass characteristic: the voltage gain is 0 for $\omega =0$, while it has a constant non-zero value for $\omega \to \infty$. Characteristic parameters for a high pass filter are the “high frequency” signal transfer and the corner frequency:

Note that for a current-to-current signal transfer or for a voltage-to-current transfer the corner frequency is identical to the one derived above. This can readily be seen using Norton-Thévenin equivalents.

5.2.4 Maximizing gain

Above, an expression for the minimum attenuation when coupling amplifier stages, $H(\infty )$, is shown when assuming both a source voltage and targeting an input voltage into the amplifier. The expressions for $H(\infty )$ are however different if this voltage-to-voltage transfer is not assumed. For example for an input current-to-voltage transfer $H{(\infty )}_{\mathit{iv}}=\frac{R_{\mathit{in}1}\cdot R_g}{R_{\mathit{in}1}+R_g}$. For maximum gain it can readily be derived that

• the -3dB corner frequency should be sufficiently below the lowest signal frequency
• for voltage-to-voltage transfer $R_{\mathit{in}1}>>R_g$
• for current-to-current transfer $R_{\mathit{in}1}<<R_g$
• for current-to-voltage transfer $R_{\mathit{in}1}$ and $R_g$ must be large
• for voltage-to-current transfer $R_{\mathit{in}1}$ and $R_g$ must be small

5.3 Other useful circuits

5.3.1 Voltage source

The most important property of a voltage source is its low output resistance. From table 1 and table 2 it follows that the emitter-follower (CCC) and source-follower (CDC) are the closest to a voltage source: they have the lowest $r_{\mathit{out}}$ of all basic amplifiers. Drive these circuits with a voltage source having a source resistance $R_G$, then output resistance of the CCC and CDC is

$$\begin{array}{rcll}& r_{\mathit{out},\mathit{CCC}}=& R_E∕∕\left(\frac{{\alpha }_{\mathit{fe}}}{g_m}+R_g\right)∕∕\left(\frac{\frac{{\alpha }_{\mathit{fe}}}{g_m}}{\frac{{\alpha }_{\mathit{fe}}}{g_m}+R_g}\right)\cdot \frac{1}{g_m}& \\ & r_{\mathit{out},\mathit{CDC}}=& R_S∕∕\frac{1}{g_m}& \end{array}$$

For both the CCC and the CDC, as a decent worst-case approximation of the output resistance is then $r_{\mathit{out}}=1∕g_m$.

Voltage source with a finite output resistance a) with an NPN b) with an NMOS transistor

It follows from $r_{\mathit{out}}=1∕g_m$ that reducing this output resistance can be done by increasing the transistor’s transconductance. This is turn can be accomplished by increasing the transistor’s bias current. If this increase in current is not acceptable, the only option is to add design degrees of freedom and use these: this boils down to increasing the circuit complexity.

Using the definition $g_m=i_{\mathit{out}}∕v_{\mathit{in}}$, another way to increase $g_m$ is to replace the single transistor by a voltage amplifier + transistor which yields $g_{m,\mathit{overall}}=A_v\cdot g_m$. The resulting circuit — with output resistance $R_{\mathit{out}}=1∕(A_v\cdot g_m)$ — is shown below. A proper analog lab power supply uses this principle, without coupling capacitors since it has to be a DC source.

Improved voltage source with $r_{\mathit{out}}\mathit{\prime \cong }{R}_E∕∕\frac{1}{A\cdot g_m}$

5.3.2 Current source

An ideal current source has an infinite output resistance. A good starting point for the design of a real current source would be a basic circuit that already has a relatively high output resistance: a CEC or CSC. In calculating the output resistance of a CEC or CSC, we assume that the bias point is set by a (source or emitter) degeneration resistance. Furthermore, since the output resistance is of importance, we must take the output resistance of the transistor, $\mu ∕g_m$ into account.

Current source a) with BJT b) with MOS c) SSEC of both

The bias current for both circuits in the figure is determined by the (impedance of the) bias source at the input, the degeneration resistor and the characteristics of the transistor. For a current source, this current has to be as constant as possible: the output resistance must be as large as possible. Using figure c) we get (for the BJT case):

$$\begin{array}{rcll}& & r_{\mathit{out}}=\frac{v_{\mathit{cc}}}{i_c}& \\ & & i_c=g_m\cdot v_{\mathit{be}}+\frac{v_{\mathit{cc}}-v_E}{\mu ∕g_m}& \\ & & v_{\mathit{be}}=-v_E& \\ & & v_E=i_c\cdot (\frac{{\alpha }_{\mathit{fe}}}{g_m}∕∕R_E)& \\ & & r_{\mathit{out}}=\frac{\mu }{g_m}+(\mu +1)\cdot (\frac{{\alpha }_{\mathit{fe}}}{g_m}∕∕R_E)& \end{array}$$

The output resistance of the circuit is the sum of the output resistance of the transistor and the multiplied degeneration resistor (for the BJT in parallel to ${\alpha }_{\mathit{fe}}∕g_m$).

5.3.3 Current mirror

For a number of applications (in circuits) a sort of copy-machine comes in handy, for example for re-using or distributing signals or bias settings. For copying a voltage, we can use a voltage buffer block with a unity voltage gain⁴³.

A solution is using a current source circuit as described in section 5.3.2. For multiple DC current sources, we might just take that current source circuit a number of times, see the left hand side in the figure below. As presented on the right hand side, we can also copy the gate voltage to the rightmost transistor, which “saves” us a bias circuit. As discussed earlier, the value of the degeneration resistor can be chosen freely, for instance $0\mathrm{\Omega }$ may be a convenient value.

Methods for generating multiple currents

Noting that the current-voltage relation of a transistor is monotonous, a convenient method to create a (gate-source) voltage that causes a certain drain current is using its inverse function. It sounds complicated, but it isn’t. For example, for the BJT we have:

$$i_C=f(v_{\mathit{BE}})\iff v_{\mathit{BE}}=f^{-1}(i_C)$$

which we can use to replicate a current by using

$$i_{C,\mathit{out}}=f(f^{-1}(i_{C,\mathit{in}}))$$

A number of circuit that implement this is shown below. These circuits are called current mirrors .

Some current mirror circuits

Again, the value of the degeneration resistance can be chosen freely: they influence both the output resistance and the required voltage headroom. Obviously, we can also create current mirrors with PMOS transistors and PNPs. Even more so, any active element with an arbitrary monotone function between output current and input voltage will do for a current mirror. A number of characteristics of current mirrors are calculated below.