8 Basic internal circuits for opamps

8.1 Introduction

Chapters 6-10 analyzed, synthesized and showed a lot of circuits that use operational amplifiers (opamps). In those chapters, a lot of attention was paid to the external behaviour (bandwidth, amplification, output impedance, etc) of an opamp, but little to none went into their internal structure. In this chapter, the internal circuits of opamps are discussed.

As seen before, there are many requirements for an opamp, including:

• an opamp has to operate on a (typically small) differential input signal. In other words: it must have a differential input stage, that works especially well for small signals.
• the voltage gain of the opamp must be very large.
• the input impedance must be sufficiently high.
• the output impedance must be sufficiently low.
• the transfer function must be first order dominant, due to the possibility of instability when operated by persons that are not paying attention (or that are insufficiently educated).
• any non-ideal properties, like offset and noise, must be as small as possible.

With a circuit containing only a single transistor, as discussed in chapter 5, usually one cannot satisfy a set of requirements on gain, bandwidth and impedances at the same time. In the context of this chapter, a major issue for these basic amplifier circuits is the lack of a differential input stage for small signals, and combining that with high gain and with a sufficiently low output impedance.

Like in chapter 5, conflicting requirements can be circumvented by using multiple amplification stages⁵⁵ . Some stages that can be used in opamps are identical to circuits in chapter 5, while others are specifically catered to their specific task in the opamp. The general construction of an opamp is shown in Figure 8.1: an input circuit that satisfies all the input requirements, an output stage that does the same for the output and something in between that completes the total behaviour.

First of all, the input stage will be discussed in §8.2. This circuit is unlike any other that has been dealt with in this book so far. Input stages operate on a differential input voltage and usually have a differential output current, that is often converted to a single-ended current to be processed further. This (possible) conversion is dealt with in §8.3.

The output current of the input stage is amplified and converted into a voltage in an intermediate stage; these stages are discussed in §8.4. To correctly operate an external load, dedicated output stages are often needed; these are discussed in §8.5. Finally, bandwidth limitations are dealt with in §8.6.1.

8.2 The input stage

The input stage of an opamp must meet a number of requirements, which follow from the practical applications of an opamp. The input stage:

• must operate on a (typically small) differential input voltage

  $$v_{\mathit{DIFF}}=v_{+}-v_{-},$$

  that can be either positive or negative and that can be at DC or that can be a fluctuating signal.

• should be insensitive for the common-mode part, or average pat, of the input signal

  $$v_{\mathit{COMMON}}=\frac{v_{+}+v_{-}}{2}.$$

  Being insensitive means that for example for input voltages $\{v_{+}=0.001,v_{-}=-0.001\}$ the response of the opamp must be the same as for input voltages $\{v_{+}=2.001,v_{-}=1.999\}$.

• must have an output current or voltage that is a measure (ideally proportional) for the differential input voltage.

From the first requirement, it follows that the circuits in chapter 5 cannot be used as input stages for an opamp: they do operate on small signal variations, but these small variation must be about a (non-zero) bias voltage. The left hand side circuit in Figure 8.2 illustrates this problem: here the differential input voltage is directly applied to the NPN’s base and emitter terminals which results in extremely poor biasing and hence in extremely poor transconducatance for very small $v_{\mathit{DIFF}}$, see also §3.1. Using an MOS transistor or an PNPs instead of the NPN does not solve the issue.

The problem sketched above can be solved using decoupling capacitors as was done in chapters 4 and 5: in that case, the input voltage does not need to be close to the bias level. For example, we might bias and drive the transistor using the circuit on the right hand side in Figure 8.2. Here the biasing circuitry is shown in grey. However, these types of circuits have a low gain for low frequencies — actually zero for DC — which is not acceptable for opamps.

8.2.1 Symmetry requirement

As shown before, a single transistor circuit cannot implement a stage that processes arbitrary differential signals — from DC to high frequencies — symmetrically. From the definitions of “differential” and “common”:

it can be seen that the differential input signal to amplify, is symmetrical around the common part of the input signal. To properly (symmetrically) operate on something that is symmetrical, one usually needs something that is also symmetrical. A single transistor circuit, sadly, is not.

There are multiple ways to create a symmetrical circuit, that can operate on small differential input voltages, and that outputs a symmetrical output current as a (symmetrical) function of the input voltage. This book will deal with a few relatively simple circuits; more complex circuits are typically variations on these basic circuits.

8.2.2 First implementation and its issues

Assuming the use of asymmetrical components (like MOS transistors, BJTs or any other electrically amplifying component), it is possible to realize symmetric functionality with 2 of those components. From the requirements for symmetry and the use of transistors, it follows immediately that (in the case of a BJT):

• both input signals must be connected to either the emitters of the transistors, or to their bases
• the signal path through the input stage (for example from the positive input to the negative input) must contain both a $v_{\mathit{BE}}$ and a $-v_{\mathit{BE}}$.

A possible implementation of this is given in Figure 8.3, shown with NPNs and PNPs.

The transfer function from differential input voltage to differential output current for the NPN version is

Figure 8.4 shows the relation in (8.1) for four levels of $v_{\mathit{COMMON}}$. The $v_{\mathit{COMMON}}$ is increased with — each time — 60 mV going from curve (a) to (b) to (c) and to (d). Note that the transfer function heavily depends on the $v_{\mathit{COMMON}}$.

This circuit does have a some (related) problematic properties. Firstly, the supply current in the circuit is strongly dependent on $v_{\mathit{COMMON}}$, which is obvious from (8.1) if we set $v_{\mathit{DIFF}}=0$:

This strong dependency of the current $i_{\mathit{TOT}}$ on $v_{\mathit{COMMON}}$ is also the cause for the second problem of this circuit: the — small signal and large signal — transfer function $i_{\mathit{OUT}}(v_{\mathit{DIFF}})$ depends strongly (exponentially) on $v_{\mathit{COMMON}}$:

It can be concluded that the circuit in Figure 8.3 actually is a differential stage: it outputs a differential current that is a reasonably nice function of the differential input voltage. However, it does have a number of issues that follow from its strong dependency on the common mode level of the input voltage.

The MOS equivalents of the circuits in Figure 8.3 have pretty much the same behaviour as the BJT versions that are discussed: these, too, have a strong dependency on the common input signal. Interestingly, assuming square law operation for the MOS transistors, the MOS versions have an output current that is exactly proportional to the differential input voltage.

8.2.3 Second (widely used) implementation

The circuit shown in Figure 8.3 would suffice as an input stage, if we make sure that the (bias) currents through both transistors are independent on $v_{\mathit{COMMON}}$. The usual way to make a current independent on a voltage is to use a current source. This results in the following input stages (which are obviously all equivalent) that are essentially the ones in Figure 8.3 biased from a so-called tail current source at their source or emitter nodes

In this book, the large signal transfer function is pretty much never used. A few relevant properties of this transfer function, like slope around $v_{\mathit{DIFF}}=0$ and maximum output current, are presumed to be easily calculated.

For the 4 circuits given in Figure 8.5, the large signal transfer functions are ugly, complex and also not very relevant (which latter point is nice). When using these input stages in an opamp, only two situations usually occur⁵⁶ :

• if the opamp is operating linearly, and the gain is large, the input signal of the opamp (applied to the input stage) will be very small. In that case, only the behaviour of the input stage around $v_{\mathit{DIFF}}=0$ is important: this is the small signal behaviour. It is usually too much work to calculate small signal aspects through a large signal derivation⁵⁷ .
• if the opamp is operating non-linearly, the input signal will be relatively large. Also in that case, the large signal transfer function is not relevant because the output current for this situation usually is clipped to one of the two extreme values. It is usually sufficient to know these clipping limits.

Because the input stage is designed to operate on small (differential) signals, this type of circuit is usually called differential stage (or, in the case where 2 transistors are used: differential pair). Being symmetrical, their behaviour around the point of symmetry ($v_{\mathit{DIFF}}=0$) is symmetrical. With small input signals, this translates into reasonably linear behaviour.

With large voltage differences $v_{\mathit{DIFF}}$, one of the transistors will conduct almost no current, and the other conducts almost all tail current. In other words: with large input signals, the differential output current will be $\pm I_{\mathit{TAIL}}$.

In Figure 8.6, the (large signal) transfer functions of a BJT differential pair and of a MOS differential pair are given. Both are S-shaped curves, which have $\pm I_{\mathit{TAIL}}$ as maximum and minimum. However, there are also differences between the large signal behaviour of BJT and the MOS versions:

• With the BJT differential pair, the largest values ($i_{\mathit{OUT}}=\pm I_{\mathit{TAIL}}$) are reached asymptotically, wherein the MOS pair these values are reached at $v_{\mathit{DIFF}}=\sqrt{2I_{\mathit{TAIL}}∕K}$.
• The large signal behaviour of a BJT differential pair is not dependent on a property of the BJT, as long as both transistors are equal. In the MOS case, the curve depends on the K factor of the transistor. A lower K factor leads to a weaker S-curve as can be seen from e.g. the large signal transfers derived earlier.

The curves in Figure 8.6, also show that the currents through the individual transistors are scaled and shifted (by $I_{\mathit{TAIL}}∕2$) versions of the total output current. Note that this is a result of the symmetry in the circuit.

8.2.4 Small signal behaviour

Differential pairs are used as input stages for opamps. For opamps that are used in linear (non-switching) applications, the input signal is usually very small, and the small signal behaviour of differential pairs is important. For two N-type differential pairs, both the circuit schematic and its small signal equivalent are given in Figure 8.7. These SSECs will be used to derive small signal properties of differential pairs.

Note that the MOS version of the small signal equivalent circuit has an apparent floating voltage node: only two voltage controlled current sources are connected to it. At first instance this configuration may seem strange, but the voltage dependency of the current sources make derivations surprisingly simple⁵⁸ .

8.2.5 BJT differential pair: transconductance

The most important property of a differential pair is its transconductance about $V_{\mathit{DIFF}}=0$. In the case of the small signal equivalent circuit for the BJT differential pair in Figure 8.7, a derivation for $v_{\mathit{DIFF}}\approx 0$ that explicitly leverages symmetry can be:

A different derivation — without explicitly using symmetry — can be:

When put into words, bottom line, the transconductance of a BJT differential pair is equal to the transconductance of the individual transistors in the pair. It can be derived that this has to be the case in these kinds of symmetric circuits. As direct consequence it follows that $i_{\mathit{cl}}=-i_{\mathit{cr}}$: the small signal collector currents do not flow through the (small-signal) base-emitter resistances due to symmetry.

8.2.6 BJT differential pair: input impedance

The input impedance of a differential pair with input voltages around $v_{\mathit{DIFF}}\approx 0$V, can be derived in a way similar to the one discussed above:

Due to symmetry in the differential pair, the small signal base current have the same (absolute) values but opposing signs: $i_{\mathit{bl}}=-i_{\mathit{br}}$. Effectively this means that the input impedance equals the two base resistances in series.

8.2.7 MOS differential pair: transconductance

For small signal transfer functions, a MOS transistor behaves identically to a BJT with an infinite current gain factor ${\beta }_{\mathit{fe}}$. Then, the transconductance of a MOS differential pair follows directly from (8.4) by letting ${\beta }_{\mathit{fe}}\to \infty$: $g_{m,\mathit{pair}}=g_{m_{\mathit{transistor}}}$.

8.2.8 MOS differential pair: input impedance

From (8.5) and substituting ${\beta }_{\mathit{fe}}\to \infty$, it follows that $r_{\mathit{in}}\to \infty$. Note that the input impedance — if the MOS transistors’ $c_{\mathit{GS}}$ is not neglected — is $z_{\mathit{in}}=2∕\mathit{j\omega }{c}_{\mathit{GS}}$.

8.2.9 Small signal behaviour with a non-ideal current source

In the previous subsections, the (ideal) small signal behaviour of differential pairs was derived. These differential pairs assume an ideal current source that is usually called a tail current source. In actual circuits, a (tail) current source is made using, for example, a MOS transistor with a constant $V_{\mathit{GS}}$ (see §5.3.2), or a resistor. In the figure below, an NMOS differential pair with a non-ideal tail current source is shown, together with the corresponding small signal equivalent circuit. Resistor $R_{\mathit{tail}}$ models the output resistance of the current source implemented by the right hand side NMOS in the current mirror in the figure.

An NMOS differential pair with a non-ideal tail current source and

the small signal equivalent circuit.

$$

The transconductance of the differential pair is easily calculated from the small signal equivalent circuit. The resulting expression is (again):

$$\begin{array}{rcll}{g}_{m,\mathit{diffpair}}& =& g_m& \end{array}$$

where the transconductance of transistors depends on the bias current of the transistors, and therefore dependent on the total tail current. In contrast to when using an ideal tail current source, now the tail current is dependent on the common input signal, due to the presence of a finite $r_{\mathit{tail}}$.

The effect of $r_{\mathbf{tail}}$ and the common input signal on the output current is easily calculated for $v_{\mathit{DIFF}}=0$V. On grounds of symmetry in the circuit and in the input signals, the drain currents of the transistors in the differential pair are identical. The output current $i_{\mathit{out}}=i_{\mathit{dl}}-i_{\mathit{dr}}$ is therefore equal to 0. If the circuit is asymmetrical for any reason, for example due to unequal transistors in the pair or because $v_{\mathit{DIFF}}\ne 0$, there is also an output current component resulting from $v_{\mathit{COMMON}}$.

8.3 From input stage to intermediate stage

In §8.2, input stages were discussed, and these input stages are usually differential pairs as shown in Figure 8.5, or variations on them. For these kinds of differential stages, the transfer functions were calculated in multiple ways, always assuming that the output signal is $i_{d1}-i_{d2}$: a differential output current.

These differential output currents are then (in an arbitrary order) amplified and converted to a voltage. Because the differential output current consists of 2 currents, and usually the output signal of the opamp is 1 voltage, somewhere there has to be a transition from differential to “single-ended”. This is the subject of this subsection, assuming a MOS differential pair as an vehicle. Figure 8.8 shows an NMOS differential pair with several forms of conversion from differential current to single current.

To easily recognize the various parts of the circuits, the NMOS differential pairs are drawn over a grey background. The four example circuit implementations are briefly discussed below.

8.3.1 Throwing away half the current

The simplest way to make a single-ended current from a differential current, is to simply throw away one of the differential current components. This has been done in the simplest possible way in Figure 8.8a. For an ideal differential pair, the output current (note the direction of the output current) for small input volages is

where $g_m$ is the transconductance of the transistors in the differential pair. The small signal transconductance of the total circuit in Figure 8.8a is hence

8.3.3 Subtracting currents

To use the differential output current of a differential pair, the two drain currents $i_{\mathit{Dl}}$ and $i_{\mathit{Dr}}$ can be subtracted from each other. In this case, the common part in the currents — $I_{}\mathit{TAIL}∕2$ — cancel and the differential currents add.

Adding currents is easy, as is reversing a current’s direction (using the current mirror in §5.3.3). Consequently, subtracting currents is also easy: first invert one component with a current mirror, and then add both currents. A corresponding circuit is shown in Figure 8.8b. The output current is (assuming an ideal differential pair and an ideal current mirror):

Note that for proper operation, all transistors in the circuit schematic must operate as intended. Usually this implies that all transistors should operate in (strong inversion) saturation. Similar to the case with single-transistor amplifiers, this limits the

• (allowed) input voltage range. Assuming small differential voltages this turns into limits to the common mode voltage in the input voltages
• (allowed) output voltage range, to keep the rightmost two transistors in (strong inversion) saturation.

8.4 Intermediate stages

The input stage of an amplifier is usually a differential pair, which has a voltage input and a current as an output. The output signal of an opamp is in the voltage domain while the overall voltage gain of an opamp should be a large as possible. Therefore another amplification stage, which converts the current to a voltage and that preferably has a large transresistance ($v_{\mathit{out}}∕i_{\mathit{in}}$) is needed. This is the function of the intermediate stage, which is dealt with below. Often (but not always), an output stage is required after the intermediate stage, in order to reduce the opamp’s output impedance. Those kinds of output stages are dealt with in §8.5.

The most important requirements for the intermediate stage are:

• a large (trans)resistance $\frac{v_{\mathit{out}}}{i_{\mathit{in}}}$, to get a large overall gain for the opamp
• an input voltage range that allows the preceeding input stage to work properly
• a sufficiently low output resistance, which may be accomplished by using an additional output stage.

Like for the other stages, there are many possibilities for the intermediate stage. A few examples, increasing in complexity, will be discussed here. Assuming these basic configurations, variations on them are easier to understand and design.

8.4.1 Intermediate stage (not) using a resistor

The most simple implementation of a voltage to current converter is a resistor. If a resistor is used as an “intermediate stage”, the resulting opamp, using an input stage with an NMOS differential pair and a PMOS current mirror, is shown in Figure 8.10.

The DC voltage source with value $V_{\mathit{BIAS}}$ is needed to keep $M_2$ and $M_4$ in saturation for small $v_{\mathit{DIFF}}$. The small signal output voltage of this circuit is

The resistance $R_{\mathit{load}}$ can be applied explicitly, or can consist of the (non ideal) finite output resistances of the MOS transistors. If only the output resistances of the transistors in the mirror are present, the small signal equivalent circuit of the schematic in Figure 8.10 is shown in Figure 8.11. The small signal output voltage, assuming a symmetric differential pair and current mirror, is then

If the output resistances of the transistors in the differential pair are also included, the result is similar. This is also reflected in the very similar (8.8) and (8.9).

8.4.2 Intermediate stage using a CEC or CSC

A somewhat more complex intermediate stage could consist of an active element as a load and extra gain stage. In this way, for example the circuit n Figure 8.12 may result. In this circuit, the current flowing from the combination of differential pair and current mirror is used to drive a PNP in a CEC configuration. Note that compared to Figure 8.10 the positive input and negative input swapped, due to the negative voltage gain of the CEC stage.

Performing calculations on this circuit can be done in several ways:

• by making a (big) small signal equivalent circuit for the whole circuit, and performing calculations on it. This is a lot of work, because it will consist of many components and the complexity (or workload) of solving a linear set of equations increases in general rapidly with the number of equations.
• subdividing the circuit into smaller subcircuits, performing calculations on those, and assembling those into one overall equation. Note that you may have to take input and output impedances of stages into account.
• examining the circuit as-is (not recommended).

Below, the second option is assumed. As simplification, it is assumed that output conductances of all transistors can be neglected, and that the differential pair and mirror are symmetric. Then — without redrawing small signal equivalent circuits for the various parts of the circuit in Figure 8.12 — for the circuit bits in the three grey areas

• the small signal transfer for the NMOS differential pair is

  $$\begin{array}{rcll}{i}_{\mathit{dl}}-i_{\mathit{dr}}& =& g_{m,\mathit{diffpair}}\cdot v_{\mathit{diff}}& \end{array}$$

• The transfer function of the PMOS current mirror is

  $$\begin{array}{rcll}{i}_{\mathit{out}}& =& i_{\mathit{in}}& \end{array}$$

• For the combination of NMOS differential pair and PMOS current mirror, this leads to:

  $$\begin{array}{rcll}{i}_{\mathit{Dl}}-i_{\mathit{Dr}}& =& g_m\cdot (v_{+}-v_{-})& \end{array}$$

• The intermediate stage consisting of a CEC converts its input current into an output voltage. There are several equivalent ways to calculate the transfer function. For example, you may calculate the (small signal) input voltage as a function of the input current which, together with the voltage gain, leads to the transfer function of the intermediate stage. For simplicity (of interpreting the result), an (combined) output resistance at the collector node equal to $r_{\mathit{out}}$ is assumed.

  $$\begin{array}{rcll}{v}_{\mathit{out}}& =& r_{\mathit{out}}\cdot {\beta }_{\mathit{fe}}\cdot i_{\mathit{in}}& \\ & =& r_{\mathit{out}}\cdot \frac{{\beta }_{\mathit{fe}}}{g_m}\cdot g_m\cdot i_{\mathit{in}}& \end{array}$$

  Note that the first equation assumes current gain, while the second one assumed $i\to v$ conversion at the small signal base-emitter resistance and subsequent transconductance. Of course the bottom line results are identical.

Combining the transfer function of the three parts, and noting that (for simplicity reasons) the output impedances of the differential pair and of the current mirror are infinite, the overall small signal transfer function is

The various small signal parameters (of course) depend on the large signal bias conditions. Obviously, there are many more interesting things to derive from this circuit, like $r_{\mathit{in}}$, $r_{\mathit{out}}$. These are all useful, and it is also useful to derive these yourself.

8.4.3 Intermediate stage (more complex)

Opamp circuits with more complex intermediate stages are also quite easy to examine, as long as the circuit is first subdivided in easy-to-analyze subcircuits. Figure 8.13 is an example of a slightly more complicated intermediate stage (together with a differential pair and current source). There are many ways to calculate the transfer function of this intermediate stage:

• $i_{\mathit{out},\mathit{vp}}\to v_A\to v_B\to v_{\mathit{out}}$
  this way requires the derivation of the input resistances and transfer functions of amplification stages.
• $i_{\mathit{out},\mathit{vp}}=i_{b-T1}\to i_{c-T1}=i_{b-T2}\to i_{c-T2}\to v_{\mathit{out}}$
  this is probably the fastest way. The result, of course, is identical to all other (good) approaches, but in this case, this approach leads to a minimum of work.
• many more equally fine ways can be found...

Note that in the first case, every stage (in the intermediate stage) is regarded as a voltage amplifier, while in the second case they are regarded as current amplifiers. This choice is arbitrary; when including the relations for input and output resistances, they yield identical results.

Assuming that the output resistance of all transistors is infinite, and assuming a load resistor $R_{\mathit{LOAD}}$, the small signal voltage gain of this circuit is

The first two terms of this expression are due to the non-unity (current) transfer of a bipolar current mirror. For large ${\beta {}_{\mathit{fe}}}_{,\mathit{mirror}}$ you the second term on the right hand side tends to 1 and may be ignored.

8.5 Output stages

For the opamp circuits discussed so far, the output impedance is quite high. For the circuits in section 8.3, the output signal is in the current domain: therefore, the output impedance is high. The same thing basically holds for the intermediate stages discussed in §8.4.

For a lot of applications, the output impedance of opamp circuits should be (relative to the load) low. Leveraging negative feedback, the output impedance can be reduced by a factor $(1+\mathit{A\beta })$ compared to that in the open loop configuration, but even then the output impedance may be too high to properly drive a low ohmic load.

As solution, usually an extra (last) gain stage is used to lower the output impedance. Such output stages — having a high input impedance and a low output impedance and typically having a low voltage gain — is of course not a new concept: in section 5.2 this has been dealt with extensively.

8.5.1 Requirements for the output stage

The most important requirements for an output stage are:

• the output impedance (or resistance) must be low. The exact definition of “low” depends on the application, but its resistance should at least be much lower than the output resistance of the preceeding stage.
• the input impedance of the output stage must be much higher than the output impedance,otherwise it would defeat the purpose of this stage.
• the output stage should not use a lot of power, in order to prevent self destruction due, to prevent draining batteries in no-time or just to avoid being evicted due to high electricity bills.

In section 8.5.2, the first two requirements are dealt with. Afterwards, in section 8.5.6, some attention is paid to efficiency aspects of various types of output stages.

8.5.2 Basic output stages

In section 5.1.7, various aspects of the 3 basic configurations using BJTs have been summarized. The summary for corresponding MOS variants is given in section 5.1.7. From the summaries, it is clear that especially the CCC — a.k.a. the emitter follower — and the CDC — a.k.a. the source follower — are good candidates for output stages: these circuits have a high input impedance and have a low output impedance. These circuits will first be examined for use as an output stage in opamp circuits.

8.5.3 CDC output stage

One of the most simple output stages for opamps is the source follower with tail current source; a schematic of such an opamp circuit is given in Figure 8.14. Note that in order to examine the entire opamp circuit, it has been subdivided into 4 parts: a differential pair, a current mirror, an intermediate stage and the CDC output stage. It is assumed that the output impedance of the pnp is $r_{\mathit{ce},\mathit{out}}$ and that there is not extrnal load attached to this opamp.

The small signal gain of this opamp can be calculated by e.g. determining and multiplying the small signal transfer functions of each subcircuit. Note that the effects of input and output impedances should be properly included! The result, for the circuit in Figure 8.14, is:

The small signal output resistance of the opamp circuit in Figure 8.14 can be calculated in multiple ways. For the derivation below, a small signal voltage source drives the output port; the output impedance is then calculated as $z_{\mathit{out}}=v_{\mathit{out}}∕i_{\mathit{out}}$. Note that for this approach, the only independent source is the one driving the output port; all other independent sources have to be set to 0.

Inspection of the circuit in Figure 8.14 shows that the small signal $i_{\mathit{Dl}}-i_{\mathit{Dr}}=0$. Consequently the small signal collector current of the pnp is also 0. Therefore, the small signal circuit equivalent circuit — to calculate $z_{\mathit{out}}$ assuming driving the output node — is the one on the right hand side in Figure 8.15.

It can be derived that for finite $r_{\mathit{out},\mathit{pnp}}$, the output resistance of the opamp circuit in Figure 8.15 is

while for $r_{\mathit{out},\mathit{pnp}}\to \infty$

Quite similar results follow when using a PMOS CDC or if a NPN or PNP CCC is assumed as output stage. Be aware that the output impedance is purely a small signal output impedance. At significant (relative to the bias current) output current fluctuation, the (then locally defined) small signal output impedance may change significantly.

Non-small signal excitation example
The output impedance as derived above is only valid for small signal excursions where the current in the NMOS transistor does not varies significantly. Furthermore, it is the output resistance of the opamp itself, not that of a circuit including the opamp in a feedback configuration. Because the output stage op the opamp is meant to drive relatively low-ohmic loads at significant voltage excursions, the small signal approximation may not hold.

Let’s assume that the opamp in Figure 8.15 has a high voltage gain and that it is used in unity-gain mode. In this mode, the small signal voltage gain is

$$H(\mathit{j\omega })=\frac{A(\mathit{j\omega })}{1+A(\mathit{j\omega })}$$

which closed loop signal transfer is close to 1 as long as the gain of the opamp is high. This high gain condition depends — among other — on the gain and output impedance of the output stage of the opamp. Now, assuming

• the CDC output stage as in Figure 8.15
• with a bias current of 1 mA
• with a K-factor $20\mathit{mA}∕V^{-2}$ for the NMOS transistor
• with an $R_{\mathit{LOAD}}=1k\mathrm{\Omega }$ load transistor (DC decoupled)
• a sinusoidal input voltage $V\cdot \sin <!--\; FUNCTION\; APPLICATION\; -->(\mathit{\omega t})$

the drain current in the NMOS transistor is the sum of the bias current $I_D$ and the signal current $i_S=V∕R_{\mathit{LOAD}}\cdot \sin <!--\; FUNCTION\; APPLICATION\; -->(\mathit{\omega t})$. The output resistance of the CDC — and that of the opamp — across the excursion is then

$$\begin{array}{rcll}& r_{\mathit{out}}(v_{\mathit{out}})& \approx \frac{1}{g_m(v_{\mathit{out}})}& \\ & & g_m(v_{\mathit{out}})=\sqrt{2\cdot K\cdot \left(I_D+\frac{v_{\mathit{out}}}{R_{\mathit{LOAD}}}\right)}& \\ & r_{\mathit{out}}(v_{\mathit{out}})& \approx \frac{1}{\sqrt{2\cdot K\cdot \left(I_D+\frac{v_{\mathit{out}}}{R_{\mathit{LOAD}}}\right)}}& \end{array}$$

The figure below shows in red the drain current in the NMOS transistor as a function of $v_{\mathit{OUT}}$, for the aforementioned conditions. In blue is the (local) $r_{\mathit{out}}$ as a function of the output voltage. For small signals around the bias point, the drain current is close to $I_D=1\mathit{mA}$ and the output impedance of the output stage is about $160\mathrm{\Omega }$; this point is marked by the blue dot in the graph.

Note that for $v_{\mathit{OUT}}=1$, the drain current is doubled with respect to $v_{\mathit{OUT}}=0$, resulting in a lower output resistance of the output stage of the opamp. Towards higher output voltages, the (local) output resistance decreases.

(red) $I_D(v_{\mathit{OUT}})$ and (blue) $r_{\mathit{out}}(v_{\mathit{OUT}})$ of the opamp in Figure 8.15 for

the conditions listed above, as a function of output voltage (excursion).

$$

Towards negative output voltages, the drain current of the NMOS transistor decreases, and is zero at $v_{\mathit{OUT}}=-1V$. There, the output resistance goes to infinity. The output stage does not work properly for excursions above $V_{\mathit{max}}=-I_D\cdot R_{\mathit{LOAD}}=-1V$.

Going to PMOS, PNP or NPN output stages with the same bias current level (and for the PMOS the same $|K$) yields similar $r_{\mathit{out}}(v_{\mathit{OUT}})$ curves. Note that the BJT-versions have lower output resistances, and note that N-versions and P-versions are merely mirrored in the y-axis.

The output resistance of opamps similar to that in Figure 8.15 with an

(blue) NMOS, (red) NPN, (green) PMOS, (black) PNP output stage

for the conditions listed above, as a function of output voltage (excursion).

$$

From this, two methods arise to make sure the output resistance remains low for relatively large — positive and negative — output currents:

• use a very large bias current, so that any output current causes a small relative change of current through the output transistor. It is clear that this solution costs a lot of power.
• change the circuit in such a way, that the current through transistors can never (or not easily) get very small. Actually, this can only be done by letting the transistors deliver a signal current which increases the total current. If you consider that a signal is bidirectional while the current in transistors is unidirecctional, it follows that this requires at least 2 transistors with complementary behaviour... Leading to a slightly more complicated output stage.

8.5.4 Slightly less simple output stages

As shown in §8.5.2, basic output stage that have relatively low output impedance (e.g. CDC or CCC stages) can be used as proper opamp output stage, as long as the current in the transistors in that stage remains sufficiently high for any output voltage. To be able to drive low ohmic loads this then would require sufficiently large bias currents. Noting that the output current can either increase the current in the transistor (in CCC or CDC) or decrease it, depending on its direction, a more power efficient way to make output stages can be deviced. A first implementation for this is given below, combining two complementary CDC circuits:

An opamp circuit with a “symmetric” or complementary output stage.

$$

Note that the output stage of the opamp schematic is basically an NMOS and PMOS CDC in parallel. Here, the two current sources are in series between the supply nodes. Assuming that they have the same value, these current sources only sink current and have no use whatsoever for the circuit. Consequently, these can be deleted, which allows to redraw the circuit schematic into:

An opamp circuit with a “symmetric” or complementary output stage.

$$

A graph showing the output stage’s transistors’ current as a function of the opamp output current is shown below. The red curve shows the drain current of the NMOS transistor, whereas the red curve corresponds to the output stage’s PMOS transistor drain current.

This dependency of the output transistors’ drain current on the opamp output current yields the following graph for the output resistance of the opamp, as a function of the opamp output current. For this circuit configuration, either the NMOS transistor or the PMOS transistor is “on” and hence determines the output resistance.

At (close) to zero output current the output resistance of the opamp is high. Note again that when using the opamp in a feedback configuration, the output resistance of that total circuit configuration is typically that of the opamp, lowered by (1+) the loop gain.

Similar to the situation with single transistor amplifiers in e.g. chapter 5.1, an lower output resistance lower than some value $r_{\mathit{out},\mathit{max}}$ for any output current level can be insured by making sure that the current in the output stage transistors is always higher than some specific value(s). Some examples are given in the next subsection, that all aim at making sure that at least one of the output stage transistors sees a sufficiently large drain current. Again similar to what was done in chapters 3-5.1 this requires a bias (quiescent) $V_{\mathit{GS}}$ for bias output stage transistors.

8.5.5 Implementation examples

To ensure that the current in at least one of the output stage transistors is sufficiently high for proper operation of the output stage, typically a sort of “floating DC voltage source” is implemented between the gates (or bases) of these.

In actual circuits, the floating DC voltage source is implemented with electronic components. Because the current through the output stage is quite dependent on the value of $V_{\mathit{DC}}$ and of (temperature dependent) properties of the transistor, the DC source $V_{\mathit{DC}}$ is often realized with transistors that behave similarly to the output stage transistors. Below, a few output stages, with different realizations for $V_{\mathit{DC}}$, and with an intermediate amplification stage using a (PNP) common-emitter circuit are shown.

The realization in a) is copied from the previous circuit schematic in this subsection, having zero bias current in the output stage transistors (with zero signal excursion). The realization in b) uses an ideal floating voltage source.

Figures c) to f) in the figure below are straightforward implementations of the DC source using compensation for temperature and production offsets. Here it is assumed that the transistor(s) that replace the floating voltage source match the output transistors, up to a scaling factor. Then the output transistors’ bias current is a scaled version of $I_X$.

A nice implementation, where $V_{\mathit{DC}}=n\ast V_{\mathit{BE}}$ with $n\ge 1$ can be realized with a BJT, is shown in f). If, for simplicity, we neglect the base current through Q, it is easily derived that $V_{\mathit{DC}}\equiv V_{\mathit{CE}}=1∕\beta \cdot V_{\mathit{BE}}$, with $\beta =R_2∕(R_1+R_2)$.

Output stages with various implementations for $V_{\mathit{DC}}$ to bias the output transistors;

an PNP CES intermediate stage is included for clarity reasons.

 

The large signal signal transfer and large-signal-dependent small signal output impedances can be derived for the presented output stages. As these are large signal derivations, they need to include the non-linear characteristics of the transistors which is harder than getting small signal behavior about a bias setting. Full derivations are outside the scope of this book, and usually not required. Deriving the small signal transfer and impedances in three situations is usually sufficient; these situations are for zero output current, maximum negative and maximum positive output current.

8.5.6 Power efficiency aspects of output stages

Output stages of opamps⁵⁹ are used on relatively low impedance loads. To do this correctly, relatively high output currents are needed, see for example §8.5.4, which can cause high power consumption in the output stage. In this subsection, the power efficiency of various output stages will be discussed.

8.5.7 Simple output stages: class A

The simplest output stages of opamps are usually emitter follower or source follower circuits, see §8.5.2. An example of such a circuit is given in Figure 8.14; the (large signal) output current for these types of circuits is:

If we assume that the output current is symmetrical, the highest possible harmonic output current⁶⁰ is:

The output power and the power delivered by the supply are:

The maximum value of the output voltage is determined by the supply voltage: if the output signal only just fits into the supply voltage, it holds that $V_{\mathit{out}}=\frac{1}{2}\cdot V_{\mathit{SUPPLY}}$. The maximum power efficiency of these kinds of output stages, therefore, is:

From (8.10), it follows that the maximum power efficiency of these kinds of circuits is only 25%. Note that this efficiency number can only be reached if the output signal perfectly fits into the supply voltage; for lower signal magnitudes the efficiency is lower. This low efficiency occurs in all amplifiers where the output signal is made, as described before, with only a single transistor. These types of amplifiers are the oldest and simplest in existence, and are denoted as class A. Strictly speaking, class A stands for an amplifier where the output transistor(s) drive the load for the entire duration of the signal.

8.5.8 Slightly less simple output stages: class B

In §8.5.4, a few less simple output stages were discussed, which can deliver reasonably large output currents using a bias current lower than the maximum output current. This was accomplished by using two transistors, each mainly responsible for a different part of the output signal. A number of implementations for this are shown in §8.5.4.

If, for simplicity, it is assumed that both transistors make up exactly half of the output sine, the output power and the supply power are again easily calculated:

Again, maximum power efficiency is reached at the maximum voltage magnitude:

Whereas with class A amplifiers, the maximum efficiency is 25%, that number for these amplifiers is $\pi ∕4\approx 78.5$ % which number is reached at maximum signal excusions. Amplifiers where one of two (quasi) symmetrical parts are driving for exactly 50% of the output signal are called class B amplifiers.

8.5.9 Slightly less simple output stages: class AB

In class B output stages, the two parts of the output stage drive exactly 50% of the output signal. This means that transistors in the other part of the output stage are “off” for 50% of the signal. In §8.5.4, a number of disadvantages of pure class B output stages are listed: among others the output resistance can be high at specific operating conditions. Another disadvantage (outside the scope of this reader) is that transistors are very slow at low current levels. Solving the issues that come with having transistors “off” is simple: ensuring an overlapping “on” range of both parts of the output stage. The resulting output stage is not class A, and not class B, but something in between: a class AB output stage. The maximum power efficiency of class AB, therefore, is:

8.5.10 Other output stages: class D

A different type of output stage is the class D stage. Where class A, AB and B work pretty “neatly”, a class D amplifier does not. In a class D amplifier the output switches between two discrete values, where the actual output signal is the resulting quasi-DC component which is something like the short-term average of the switched signal, where all higher components are filtered out.

If, for the basic schematic in Figure 8.16 the switching frequency (frequency of the triangle) is much higher than the signal frequency, the signal can be regarded as quasi-DC. In the system in Figure 8.16 the “on” times of switches S1 and S2 are linearly dependent on the input signal level, as is then the quasi-DC component of $v_X$. After filtering out the switching frequency and its harmonics, $v_{\mathit{OUT}}$ is an amplified version of the input signal $v_{\mathit{IN}}$.

The very nice property of this type of amplifier is that the switches are either “on” with a voltage drop of (ideally) 0V, or “off” with (ideally) no current in the switch. Consequently the power efficiency of an ideal class D amplifier is 100%. Dissipation in the control circuitry and switching losses, as well as non-ideal filtering reduces the power efficiency to typically around 90%.

8.5.11 Other output stages: class C, E, F, G, H, ...

There are many more types of output stages than those discussed just now; a large part of the alphabet has been reserved for them. The class C amplifier is essentially a class A or class B amplifier, where only a part of the input signal is actually amplified. It yields distorted output signals, similar to those in Figure 3.1, at a high power efficiency. Class E and class F amplifiers are resonant amplifiers meant to efficiency amplify narrow band signals such as radio frequency (RF) signals in power amplifiers in transmitters. Class G and H are variations on the ones mentioned before, but using a variable supply voltage.

8.6 Frequency dependencies

The combination of resistances and capacitances usually leads to bandwidth limitations. In actual transistors, many capacitances are present. In bipolar transistors these are mainly the (parasitic, unwanted) junction capacitances across the base-emitter and base-collector junctions. In MOS transistors some capacitances are fundamental while others are just parasitic, usually both are unwanted and also assumed to be parasitic. In previous chapters, parasitic capacitances were all neglected which may be acceptable at low signal frequencies. At higher frequencies they however cannot be neglected. In §8.6.1, the effect of parasitic capacitances will be analyzed and “solved” for small signals. Then, in §8.6.2, the effect of limited bandwidth on large signal behaviour will be discussed.

8.6.1 Bandwidth limitations: small signal

If the parasitic components of transistors are explicitly included in an opamp circuit, you may get something like Figure 8.17. That circuit comprises 6 transistors and 3 current sources (that may again be composed of transistors). This yields already a circuit with 16 capacitors, which makes analyses quite complex.

To analyze the behavior of this circuit, circuit can be rewritten into a much more easy-to-read form. For this, many capacitances can be replaced by single capacitances. Because this circuit has 3 internal nodes and one (not low-ohmically driven) output node there is only a low number of capacitances required that are equivalent to the 16 shown in the figure. As next step to reduce the complexity of analysis it is useful to realize that usually one frequency limitation is the worst (dominant) and that others then are not that relevant. It can be argued that:

• only the node that shows the lowest cutoff frequencies (for low-pass characteristics) is important

In the given circuit — and generally, when dealing with parasitic capacitances — parasitic capacitances usually dominantly introduce low-pass characteristics⁶¹ . For a low pass behavior due to the impedance at a node, the associated cut off frequency is ${\omega }_{-3\mathit{dB},\mathit{node}}=\frac{1}{c_{\mathit{node}}\cdot r_{\mathit{node}}}$ from which it follows that (almost) all parasitic capacitances that are between 2 low ohmic nodes, are not very relevant. The schematic of Figure 8.17 can then be reduced to that in Figure 8.18 allowing (relatively) easy calculation of small signal properties.

8.6.2 Bandwidth limitations: large signal

Bandwidth limitations have different effects on a large or small signal level. For small signals, it just shows as some kind of low pass or high pass filtering effects, which are linear effects. For large signals, however, it can cause nonlinear effects. A description is in this paragraph, using a (generally valid) example.

Assuming, for simplicity, an amplifier with dominant first order behaviour, the open loop transfer function can be given by the following relation. In this, linear behavior is assumed which allows using the frequency-domain relation.

If this amplifier is used in a configuration with negative feedback — as is often true for opamps in linear applications — the input signal of the opamp is ideally

Equation (8.13) still assumes linear behaviour of the amplifier. Having e.g. an differential pair as input circuit for an opamp, the gain $A(\mathit{j\omega })$ is both frequency and input voltage magnitude dependent. Whereas for small signals the input voltage dependency may be neglected, for large signals this is certainly not the case. For relatively large input voltages the output current of a differential pair is limited to the value of its tail current source; in that situation the small signal gain $d{i}_{\mathit{out}}∕d{v}_{\mathit{in}}$ has dropped to 0 and effectively loop gain also dropped to zero. Modelling (assuming) this as the actual limit of linear-ish behavior in a feedback system, then for an opamp similar to the one in Fig. 8.18:

leading to a maximum rate at which voltage $v_B$ at node B can change:

In this equation $C_B$ is the total capacitance at node B. This $C_B$ is composed of the capacitance across the base-emitter of $T_2$ and of the capacitance at node B due to the so-called Miller capacitor across base-collector. Assuming a small signal voltage gain of $T_2$ equal to $-A_{T2}$ then the total capacitance at node B equals $C_B=C_{\mathit{BE}}+(1+A_{T2})\cdot C_{\mathit{CE}}$. The maximum rate at which the output voltage of the opamp can change is

This maximum slope of the output voltage is called the slew rate (SR). An amplifier running into these kinds of slew rate limitations is usually said to be “slewing”.

Let’s assume that a sinusoidal signal must be amplified, using an amplifier with a limited slew rate. Then the signal frequency in combination with signal magnitude determine the maximum rate at which the signal changes in time, $\omega \cdot V_{\mathit{signal}}$. Assuming an amplifier with a single sidedly limited (too low) slew rate,

• for a fixed signal frequency, the signal amplitude must be sufficiently small not to enounter slew effects. If this is satisfied, then (sufficiently) linear operation results.
• for a fixed signal amplitude, the signal frequency must be sufficiently small not to enounter slew effects. If this is satisfied, then (sufficiently) linear operation results.

For an output sine $v_{\mathit{OUT}}=V_{\mathit{out}}\cdot \mathit{sin}(\mathit{\omega t})$, the required slew rate for a neat amplification is $S{R}_{\mathit{required}}\le \omega \cdot V_{\mathit{out}}$. If the required SR is higher than the actual slew rate of the amplifier, a part of the sine wave will see distortion, see the figure below.

The effect of a too small slew rate for the signal to be processed: slewing.