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As a first guess, let’s neglect the base current, derive the value for
for that assumption and after that determine whether this assumption was valid. From the exercise
we can readily get a number of currents and voltages:
Neglecting base current may be valid but this must be checked. ONLY if the base current is much smaller than the current in the assumption was/is valid.
As is not much smaller than , the base current cannot be ignored. Therefore a more elaborate derivation much be done taking the impact of into account!
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There is (negative) feedback that serves to stabilize the bias settings. This can conveniently be
explained using a type of flow diagram:
whereby the indicates an increase and the indicates a decrease in value.
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The (unloaded) output voltage
due to
is:
The next step is to calculate the short circuit output current due to - for this we need a new small signal equivalent circuit:
Note that for this SSEC, because appears shorted
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Reusing a previous equation for can shorten the derivation (only) a little. This leads to
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Bias = DC ,
,
and assume
This requires some rewriting: separation of variables to get a closed expression for :
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The voltage drop across
is zero (short at DC), so .
Or you can see it directly from the equivalent circuit for operation at DC in the previous
answer.
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A common emitter circuit (CEC)
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You can ignore the output impedance of the transistor as long as it is significantly higher
than other impedances at the relevant node (collector). In this case that means that
for signal frequencies.
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Set DC sources to 0 (in this circuit that is only ).
Assume that the values of reactances for which no values are specified are large. Note that
in this exercise you have to retain
and !
This allows to replace them by shorts or opens: open,
short,
short.
SSEC of the BJT (including B/C/E node identifiers)
Indicate and and redraw. Again: you should (see the description of the circuit) not replace , by shorts!
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In this answer, the output port is driven from an independent voltage source driving the
output port. The other independent sources need to be set to zero. The corresponding
small signal equivalent circuit is given below. This will be used to derive .
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Using the SSEC from question e) to calculate the voltage gain
can be done as follows.
This SSEC can be simplified by capturing and into one impedance
A derivation can be done as shown below:
Now back substitution leads to the/an answer:
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is the voltage at the base node, which generally cannot be calculated merely assuming and form a resistive divider and hence applying the formula for that. This can easily be seen in the circuit schematic depicting the voltages and currents at and around and .
From this can be derived. Formulating KCL/KVL:
leading to
Or applying superposition you get the same equation in a different appearance:
This yields:
This yields numerically
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When the signals are sufficiently small so that we can approximate the non-linear
transistor characteristics by a linear function.
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Which can be redrawn (simplified) into
To calculate the output resistance, e.g set and force a voltage at the output . Then calculate the current delivered by and apply Ohm’s law.
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The gate current (for this model) is zero which does not require any (equivalent) small
signal component. The drain current depends only on the gate-source voltage which can
be modelled with a voltage controlled current source delivering .
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Which can be simplified into:
This small signal equivalent shows that the gate is connected to ground AND that both the input signal port AND the output port have this ground in common.
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The derivation is pretty much the same as for question (c), .
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From the previously derived small signal equivalent circuit:
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Recycling the answer to the previous question:
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From
it can be derived that
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Working this out yields:
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is smaller than the assumed so the gain of the first stage will be a little lower than the numerical value derived earlier.
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Recycling the results of the previous question and combining that with one of the equations for of an MOS transistor:
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For which back substitution yields:
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You cannot ignore the base current as an
is explicitly specified.
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If this could be simplified to
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If the transistor is replaced and
the collector current and voltage gain will both decrease,but by far not by the amount by
which
has decreased. Rewriting the previously derived equation directly yields .
So decreases with as does the small signal parameter .
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The first stage gives a loaded voltage gain
The second stage gives a voltage gain
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Recycle the previously derived equation, rewrite for
:
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After replacing caps by shorts, inductors by opens, and replacing DC sources by their SS-equivalents:
After replacing the non-linear device(s) by their SSEC:
After cleaning up the winding ground wire we get the easiest SSEC: