Exercise 7.5 Stability and phase marging

To build a stabilized power supply we may use the circuit below to regulate $V_{\mathit{DD}}$ down to $v_{\mathit{OUT}}$. We assume $M_1$ works in saturation and that this transistor has infinite output resistance.

a)

To analyze the basic functionality of the circuit, at first we assume the opamp is ideal: $r_{\mathit{in}}=\infty$, $r_{\mathit{out}}=0$, $A=\infty$. For this situation, derive an expression for $v_{\mathit{OUT}}$.

For non-ideal opamps in feedback configurations, stability may be an issue. A more accurate model of the opamp is having both finite gain and limited bandwidth, leading to an opamp gain described by: $A(\mathit{j\omega })=A_0∕(1+\mathit{j\omega \tau })$. This model is to be used for questions (b)-(d).

b)

Derive an expression for the unity-gain bandwidth of this opamp in [Hz]. You may assume that $A_0\gg 1$.

c)

Derive an expression for the small signal loop gain.

Now let’s assume that we dimension $R_1$, $R_2$, $C_{\mathit{out}}$ and $g_{m1}$ in such a way that the unloaded regulator is stable and its loop has sufficient phase margin.

d)

An external current source draws a positive DC output current $I_{\mathit{OUT}}$ out of the regulator. How does this influence the phase margin? Illustrate with either an analytical proof or with a Bode plot.