7 The opamp and stability

Q 7.1

See the opamp circuit below.

The opamp is almost ideal ($r_{\mathit{in}}\to \infty$, $t_{\mathit{out}}=0\mathrm{\Omega }$), but it has a frequency dependent gain according to $A(\mathit{j\omega })=\frac{A_0}{1+\mathit{j\omega }∕{\omega }_0}$, with $A_0\gg 1$.

(a)

Derive an equation for the loop gain of this circuit.

We now define an (angular) frequency ${\omega }_1=\frac{1}{R_2\cdot C_1}$

(b)

With $A_o\gg 1$, is it possible to get a phase margin of $45°$ if ${\omega }_0={\omega }_1$?

(c)

With $A_o\gg 1$, is it possible to get a phase margin of $45°$ if ${\omega }_0\gg {\omega }_1$?

(d)

With $A_o\gg 1$, is it possible to get a phase margin of $45°$ if ${\omega }_0\ll {\omega }_1$?

(e)

Calculate for one of the cases above where $45°$ phase margin can be obtained, the corresponding/required ${\omega }_1$. The properties of the opamp are fixed.

Q 7.2

Given is the opamp circuit below. For the opamp, $r_{\mathit{in}}=1M\mathrm{\Omega }$, $r_{\mathit{out}}=75\mathrm{\Omega }$, DC voltage gain $A_{\mathit{DC}}=10^5$, open-loop unity-gain bandwidth $f_{\mathit{UG}}=$ 1 MHz, first order low-pass behavior. In the circuit, $R_1=10k\mathrm{\Omega }$.

(a)

Formulate an expression for the (open loop) gain of the opamp.

Indicate if the following statements are true or false. Motivate your answers with a proper explanation or calculation.

(b)

The absolute value of the input impedance of the circuit, $|z_{\mathit{in}}|$, is higher than or equal to $R_1$ for all frequencies.

(c)

The absolute value of the input impedance of the circuit, $|z_{\mathit{in}}|$, is higher than $R_1$ for at least one frequency.

(d)

If you connect a capacitor in parallel to the port where $z_{\mathit{in}}$ is defined in the figure, the phase margin can get very small.

(e)

If you connect a capacitor in parallel to the port where $z_{\mathit{in}}$ is defined in the figure, the gain margin can get very small.

(f)

$|z_{\mathit{in}}|$ is higher at lower frequencies than at higher frequencies.

(g)

If you connect an inductor in parallel to the $Z_{\mathit{in}}$ terminals, you may run into stability problems.

Q 7.3

See the schematic below. For the opamp, $r_{\mathit{in}}\to \infty$, $r_{\mathit{out}}=0\mathrm{\Omega }$) and the voltage gain is $A$.

(a)

Under assumption of $A\to \infty$, derive the transfer function from $v_{\mathit{in}}$ to $v_{\mathit{out}}$.

(b)

Now assume that the opamp gain has a finite frequency-independent value A. Calculate the transfer function $H(\mathit{j\omega })=v_{\mathit{out}}(\mathit{j\omega })∕v_{\mathit{in}}(\mathit{j\omega })$ for this case and draw a magnitude part of the bode plot, indicating the values of poles, zeros (x-axis) and flat parts (y-axis).

(c)

Now assume that the opamp gain has a frequency-dependent gain $A(\mathit{j\omega })=A_0∕(1+\mathit{j\omega }∕{\omega }_1)$. Determine whether the circuit has a phase margin $>45°$ for $A_0=100$dB, ${\omega }_1=2\pi \cdot 10$, $L_1=100\mathit{\mu H}$, $R_2=1k\mathrm{\Omega }$.

Q 7.4

Given is the circuit below. For the opamp, $r_{\mathit{in}}\to \infty$, $r_{\mathit{out}}=0\mathrm{\Omega }$, and the voltage gain $A$ is finite.

(a)

Derive an expression for the output impedance of the circuit (looking into the port denoted by $v_{\mathit{out}}$).

(b)

Draw the magnitude part of a bode plot of this output impedance. Indicate the values of the poles/zeros (x-axis) and flat parts (y-axis).

It appears that the opamp in this circuit actually has a frequency dependent gain $A(\mathit{j\omega })=\frac{A_0}{1+\mathit{j\omega }∕{\omega }_1}$.

(c)

Show (with calculations and/or plots) that the phase margin is larger than $60°$ for the schematic above (with frequency dependent $A$) if the circuit is unloaded (if the load impedance is infinite).

(d)

Show (with calculations and plots) that the phase margin can go to very low values for the schematic above (with frequency dependent $A$) if the circuit is loaded by a resistor $R_L$ with unknown value.

Q 7.5

To build a stabilized power supply we may use the circuit below to regulate $V_{\mathit{DD}}$ down to $v_{\mathit{OUT}}$. We assume $M_1$ works in saturation and that this transistor has infinite output resistance.

(a)

To analyze the basic functionality of the circuit, at first we assume the opamp is ideal: $r_{\mathit{in}}=\infty$, $r_{\mathit{out}}=0$, $A=\infty$. For this situation, derive an expression for $v_{\mathit{OUT}}$.

For non-ideal opamps in feedback configurations, stability may be an issue. A more accurate model of the opamp is having both finite gain and limited bandwidth, leading to an opamp gain described by: $A(\mathit{j\omega })=A_0∕(1+\mathit{j\omega \tau })$. This model is to be used for questions (b)-(d).

(b)

Derive an expression for the unity-gain bandwidth of this opamp in [Hz]. You may assume that $A_0\gg 1$.

(c)

Derive an expression for the small signal loop gain.

Now let’s assume that we dimension $R_1$, $R_2$, $C_{\mathit{out}}$ and $g_{m1}$ in such a way that the unloaded regulator is stable and its loop has sufficient phase margin.

(d)

An external current source draws a positive DC output current $I_{\mathit{OUT}}$ out of the regulator. How does this influence the phase margin? Illustrate with either an analytical proof or with a Bode plot.

Q 7.6

The figure below shows four circuits with (identical) opamps; these are marked a), b), c) and d).

The Bode plot of the voltage gain $A_{\mathit{opamp}}(\mathit{j\omega })$ of the opamps is shown in the next figure. The input impedance of the opamp is infinite, its output impedance is $0\mathrm{\Omega }$.

(a)

From the Bode plot, derive/formulate a parametric equation for $A_{\mathit{opamp}}(\mathit{j\omega })$ of the opamps. Please use this equation for voltage gain — as long as possible — in the derivations below to retain readable parametric equations.

(b)

We want the amplifier circuits to operate stable with a gain of $A_v=+10$ in the frequency range of $0\dots 10\mathit{kHz}$. Which of the configurations a through d has the largest phase margin?

(c)

Determine the phase and gain margin for the circuit of in c) in the figure.

(d)

Derive an expression for the output impedance of the circuit schemtic marked c) in the figure. Do this for the frequency domain of $0\dots 10$ kHz. Estimate first which pole(s) can be neglected for this question.