Exercise 7.4 Phase margins

Given is the circuit below. For the opamp, $r_{\mathit{in}}\to \infty$, $r_{\mathit{out}}=0\mathrm{\Omega }$, and the voltage gain $A$ is finite.

a)

Derive an expression for the output impedance of the circuit (looking into the port denoted by $v_{\mathit{out}}$).

b)

Draw the magnitude part of a bode plot of this output impedance. Indicate the values of the poles/zeros (x-axis) and flat parts (y-axis).

It appears that the opamp in this circuit actually has a frequency dependent gain $A(\mathit{j\omega })=\frac{A_0}{1+\mathit{j\omega }∕{\omega }_1}$.

c)

Show (with calculations and/or plots) that the phase margin is larger than $60°$ for the schematic above (with frequency dependent $A$) if the circuit is unloaded (if the load impedance is infinite).

d)

Show (with calculations and plots) that the phase margin can go to very low values for the schematic above (with frequency dependent $A$) if the circuit is loaded by a resistor $R_L$ with unknown value.