Small signal equivalent circuits

A signal source with output resistance

R_{g}

of

600 Ω

is connected to an amplifier circuit. We can choose from two amplifiers: one with a voltage gain

a_{v 1} = 30

and an input resistance

r_{in 1} = 6 k Ω

, the other with a voltage gain

a_{v 2} = 60

and an input resistance

r_{in 2} = 600 Ω

. The output of the amplifier remains unloaded (open).

(a): Calculate the gain from input voltage to output voltage, for both amplifier configurations.
We now place a coupling capacitor $C_{c}$ between the output of the signal source and the input of the amplifier.
(b): Calculate the value of capacitor $C_{c}$ to get a (low frequency, -3dB) cutoff frequency equal to 20 Hz. Provide the answer as a function of among others $r_{in}$ and $R_{g}$ .
(c): Draw a Bode plot (magnitude and phase) of the transfer function of the amplifier configuration including capacitor $C_{c}$ . You may assume that $r_{in} = r_{in 2} = 600 Ω$ and that $a_{v} = a_{v 2} = 60$ for this plot.

Given in the amplifier circuit schematic below.

(a): Derive an expression for the drain current $I_{D_{1}}$ expressed in terms of circuit parameters (component values, component parameters ( $K$ , $V_{TH}$ , etc.), supply voltage, etc.). Note that $v_{in}$ is a small signal voltage source with DC value $= 0$ .
(b): Draw a small signal equivalent circuit.
(c): Derive an equation for the voltage gain $a_{v} = v_{out} ∕ v_{in}$ of this circuit. For simplicity reasons, you may assume that the capacitor is low ohmic at signal frequencies.
(d): Derive an equation for the output impedance $r_{out}$ of this circuit. For simplicity reasons, you may assume that the capacitor is low ohmic at signal frequencies.
(e): Derive an equation for the output impedance $r_{out}$ of this circuit. For simplicity reasons, you may assume that the capacitor is low ohmic at signal frequencies.

The web can provide you with lots of useful information, but also with even more rubbish. You might want to build an amplifier and stumble upon: http://tymkrs.tumblr.com/post/13115454729/beta-hfe-gain-2n3904s-i-think-its-transistor What goes wrong when you follow this advice? An excerpt:

A 2N3904 transistor’s beta max value is 150 and min value is 100. When figuring out DC current gain, the beta value is part of the formula. In the sheet above, it is also known as as hFE. (hFE = beta = gain for easier understanding) So if you need to build an amplifier with a gain of 300, you set up 3 transistor stages. A good rule of thumb is to build it using the minimum beta value instead of the max: [100] + [100] + [100] = 300…So even if it’s at its minimum, it still has enough gain [150] + [150] + [150] = 450…If all of the transistors were at their max, gain = 450 If you based the gain off of the maximum beta value instead of minimum: [150] + [150] = 300…. This is possible if it works at its maximum gain BUT [100] + [100] = 200…. This wouldn’t give you enough gain! Now hFE and beta cannot be greater in value than allowed by the gain. Otherwise you get noise caused by saturation and clipping of the signal

Given is the amplifier circuit schematic below.

Derive a (parametric) equation for the input impedance $r_{in}$ of this circuit. For this question you may assume that the coupling capacitors have a negligibly small impedance at the signal frequency.

See the amplifier circuit below. Assume that

M_{1}

is biased in the square law region with drain (bias) current

I_{D 1}

. Assume inductors and capacitors can be modelled as opens and shorts for the signal frequency.

(a): Is this an inverting or a non-inverting amplifier? Motivate your answer.
(b): Draw a proper small-signal equivalent circuit.
(c): Derive an expression for the voltage gain $a_{v} = v_{out} ∕ v_{in}$
(d): Derive an expression for the input resistance $r_{in}$ .

Given is the amplifier circuit schematic below.

(a): Draw a small-signal equivalent circuit, assuming $C_{1}$ and $C_{2}$ have very low impedance at signal frequencies.
(b): Derive an expression for the voltage gain $a_{v} = v_{out} ∕ v_{in}$ .

Given is the circuit schematic of an amplifier, see below.

(a): The amplifier is driven by an ideal voltage source $v_{in}$ and the circuit itself is unloaded. Derive an equation for the frequency dependent voltage gain $a_{v} = v_{out} (jω) ∕ v_{in} (jω)$ . This equation includes the impedance of the capacitances - you cannot assume these to be (near) zero.
(b): Rewrite the previously derived equation into a standard form. This standard form lets you easily get DC-gain, high-frequency gain, poles and zeros from the expression).
(c): Draw a Bode plot (magnitude and phase) of this transfer, indicating the values of poles and zeros (on the x-axis) and the level of the flat part (y-axis).

See the amplifier circuit below. Assume that the impedance of the capacitors is very low at the signal frequency.

(a): Draw a small signal equivalent circuit of this amplifier.
(b): Derive an equation for the voltage gain $a_{v} = v_{out} ∕ v_{in}$ .
(c): Derive an equation for the output impedance of this circuit.
(d): In the questions so-far, the circuit was driven from a voltage source. Now, let’s replace that voltage source by a current source. Derive an equation for the output impedance of this circuit, assuming that the circuit is driven by a current source.

Given is the circuit schematic below. The output resistance of the MOS transistor can be assumed to be infinite. The capacitor can be modelled as a short circuit for all signal frequencies. The transistor threshold voltage equals

V_{T}

, its current factor is

K

and the transistor operates in saturation.

(a): Derive/draw a small-signal equivalent circuit.
(b): Derive an expression for the transistor’s bias current $I_{D}$ as a function of e.g. $V_{DD}$ , $V_{GG}$ , $R_{S}$ and the given transistor parameters. Note that this question is very much related to chapter 3.
(c): Derive an expression for the transistor’s transconductance $g_{m}$ as a function of e.g. $V_{DD}$ , $R_{S}$ and the given transistor parameters.
(d): Derive, using the SSEC of (a), a relation for the voltage transfer of $v_{in}$ to $v_{out}$ .
(e): Derive a relation for the input resistance of the circuit, as seen from the input source $v_{IN}$ .

The figure below shows two single transistor amplifiers.

(a): Suppose you have full freedom in choosing the supply voltage, the resistor and capacitor values, the size of the transistors (so $I_{C 0}$ for the bipolar transistor), how would you dimension/bias the bipolar circuit to achieve maximum voltage gain?
(b): Suppose you have full freedom in choosing the supply voltage, the resistor and capacitor values, the size of the transistors (the $K$ of the MOSFET), etc., how would you dimension/bias the MOS circuit to achieve maximum voltage gain?
(c): Compare the maximum achievable voltage gain, assuming the same supply voltage and compare the corresponding dimensioning for the two circuits to achieve that.

The figure below shows the symbol of a triode vacuum tube, identifying its anode (A), cathode (C) and grid (G) nodes. The heater is not shown in this symbol. The I-V relations for this device are (simplified version of the Child-Langmuir law):

\begin{array}{rcl} i_{G} = 0 \\ i_{A} = K \cdot {(v_{GC} + \frac{v_{AC}}{μ})}^{3 ∕ 2} (for v_{GC} + \frac{v_{AC}}{μ} > 0) \end{array}

where $K$ and $μ$ are device properties.

(a): Derive a proper small signal equivalent circuit for this (two-port) device, including equations relating the small signal parameters to bias settings.

The figure below shows the symbol of a pentode vacuum tube, identifying its anode (A), cathode (C), screen (S) and grid (G) nodes. The heater is not shown in this symbol. The I-V relations for this device are (simplified version of the Child-Langmuir law):

\begin{array}{rcl} i_{G} = 0 \\ i_{A} = K \cdot {(v_{GC} + \frac{v_{AC}}{μ_{c}} + \frac{v_{SC}}{μ_{s}})}^{3 ∕ 2} (for v_{GC} + \frac{v_{AC}}{μ_{c}} + \frac{v_{SC}}{μ_{s}} > 0) \end{array}

where $K$ , $μ_{c}$ and $μ_{s}$ are device properties.

(a): In its most simple application, the screen voltage is fixed to some constant and high voltage, $v_{SC} = V_{HIGH}$ . This is also assumed in the rest of this question. The pentode then effectively reduces to a device having 3 terminals (A,G,C) that see current and/or voltage changes. Derive a proper small signal equivalent circuit for this (then two-port) device, including equations relating the small signal parameters to bias settings.

The figure below shows the symbol of a PNP transistor, identifying its emitter (E), base (B) and collector (C) nodes. Including all plus and minus signs in the element equations, the I-V relations for this device are:

\begin{array}{rcl} i_{C} = I_{C 0} \cdot (e^{- \frac{q \cdot v_{BE}}{kT}} - 1) \cdot (1 - e^{- \frac{q \cdot v_{CE}}{kT}}) \\ i_{B} = \frac{i_{C}}{αfe} \end{array}

where $I_{C 0}$ is a (negative valued) device property assuming the arrows as shown in the figure and with the listed element equations. Note that a positive conventional current flows opposite of the arrows: out of the base and out of the collector node.

(a): Derive a proper small signal equivalent circuit for this pnp type BJT, including equations relating the small signal parameters to bias settings.
(b): Compare the SSEC of the pnp with that of an npn. Describe the differences (if any) in value, sign, ..., equations relating the small signal properties to bias settings, ...

4 Small signal equivalent circuits