Exercise 3.7 Biasing a circuit with an NMOS transistor

a)

An answer:

$$\begin{array}{rcll}& R_{G1}& =\frac{V_{\mathit{DD}}-V_G}{I_{\mathit{RG}1}}& \\ & & V_G=V_{\mathit{GS}}+V_S& \\ & & I_{\mathit{RG}1}=\frac{V_{\mathit{DD}}}{R_{G1}+R_{G2}}& \\ & & V_{\mathit{GS}}=V_T+\sqrt{\frac{2I_{\mathit{BIAS}}}{k}}& \\ & & V_S=I_{\mathit{bias}}\cdot R_S& \\ & R_{G1}& =\frac{V_{\mathit{DD}}-V_T-\sqrt{\frac{2I_{\mathit{BIAS}}}{k}}-I_{\mathit{BIAS}}\cdot R_S}{V_{\mathit{DD}}}\cdot (R_{G1}+R_{G2})& \\ & & =\frac{V_{\mathit{DD}}-V_T-\sqrt{\frac{2I_{\mathit{BIAS}}}{k}}-I_{\mathit{BIAS}}\cdot R_S}{V_T+\sqrt{\frac{2I_{\mathit{BIAS}}}{k}}+I_{\mathit{BIAS}}\cdot R_S}\cdot R_{G2}& \end{array}$$

This equation can of course be rewritten in many ways.

An alternative derivation can be:

Calculating the required $V_G$ from a biasing point-of-view and from the bias network (note that the gate current is zero) and equating the two:

$$\begin{array}{rcll}& V_G& =\frac{R_{G2}}{R_{G1}+R_{G2}}{V}_{\mathit{DD}}& \\ & V_G& =V_T+\sqrt{\frac{2I_{\mathit{BIAS}}}{k}}+I_{\mathit{BIAS}}\cdot R_S& \end{array}$$

Equating the two yields a proper expression for the required $R_{G2}$

b)

An answer:
Filling in the previously derived equation yields $R_{G1}=10k\mathrm{\Omega }$

Without a) it can be done with iteratively calculating voltages and currents in the circuit, following a type of Sudoku-approach. Doing so: $V_S=1V$, need $V_{\mathit{GS}}=4V$ $\to$ $V_G=5V$, so $R_{G1}=R_{G2}$

c)

An answer:
Clip: $V_D=V_{\mathit{DD}}=10V$

Saurationt: $V_D=V_{D{S}_{\mathit{min}}}+V_S=V_{\mathit{GS}}-V_T+V_S=4-2+1=3V$

Maximum swing for $V_D=6.5V$ $\to$ $V_{\mathit{RD}}=3.5V$, $R_D=3.5k\mathrm{\Omega }$