Exercise 7.4 Phase margins

a)

An answer:

$$\begin{array}{rcll}& z_{\mathit{out}}& =\frac{v_{\mathit{out}}}{i_{\mathit{out}}}& \\ & & i_{\mathit{out}}=\frac{v_{\mathit{out}}+A{v}_{\mathit{out}}}{R_1+\mathit{j\omega }{L}_2}=\frac{1+A}{R_1+\mathit{j\omega }{L}_2}{v}_{\mathit{out}}& \\ & z_{\mathit{out}}& =\frac{v_{\mathit{out}}}{i_{\mathit{out}}}=\frac{R_1+\mathit{j\omega }{L}_2}{1+A}& \\ & & =\frac{R_1}{1+A}\cdot \left(1+\mathit{j\omega }\frac{L_2}{R_1}\right)& \end{array}$$

b)

An answer:

c)

An answer:
Stability is about loop gain; for this circuit the loop gain with an infinite load impedance is $$\begin{array}{rcll}& A_{\mathit{loop}}& =\mathit{A\beta }& \\ & & =A=\frac{A_0}{1+\mathit{j\omega }{\tau }_1}& \end{array}$$

From which it follows that the phase of the loop gain is between $0°$ and $-90°$, yielding a phase margin $>90°$. The phase margin is hence also larger than $60°$.

d)

An answer:

$$\begin{array}{rcll}& A_{\mathit{loop}}& =\mathit{A\beta }& \\ & & \beta =\frac{R_L}{R_1+R_L+\mathit{j\omega }{L}_2}& \\ & & =\frac{R_L}{R_1+R_L}\cdot \frac{1}{1+\mathit{j\omega }{L}_2∕(R_1+R_L)}& \\ & & =\frac{R_L}{R_1+R_L}\cdot \frac{1}{1+\mathit{j\omega }∕{\omega }_0}& \\ & & A=\frac{A_0}{1+\mathit{j\omega }∕{\omega }_1}& \\ & A_{\mathit{loop}}& =\frac{A_0}{1+\mathit{j\omega }∕{\omega }_1}\cdot \frac{R_L}{R_1+R_L}\cdot \frac{1}{1+\mathit{j\omega }∕{\omega }_0}& \end{array}$$

The pole at ${\omega }_0$ can be at any (radian) frequency, depending on (among others) the value of the load resistor $R_L$. If ${\omega }_0<<<{\omega }_1$ or if ${\omega }_0>>>{\omega }_1$ the phase margin can be sufficient (check!). For ${\omega }_0\approx {\omega }_1$ the phase margin will be very small for large DC opamp gain values $A_0$.