Exercise 3.8 Biasing an amplifier circuit with an NMOS transistor

Given is the amplifier circuit schematic below. The capacitors have an impedance that is negligible at the signal frequency, nd the transistor is assumed to operate according to the square-law ($i_D=\frac{1}{2}K\cdot {(v_{\mathit{GS}}-V_T)}^2$).

a)

We want to set $I_{D1}=I_{\mathit{BIAS}}$. Derive a (parametric) equation for the required value for $R_S$ as a function of various component values and component properties.

b)

For $I_{D1}=I_{\mathit{BIAS}}=4\mathit{mA}$. $V_{\mathit{DD}}=10V$, $K=2\mathit{mA}∕V^2$, $V_T=1V$, $R_{G1}=220k\mathrm{\Omega }$, $R_{G2}=220k\mathrm{\Omega }$, calculate the numerical value of the required $R_S$. Calculate the required value of $R_S$.

c)

To have some signal swing at the output and to have the transistor operating in saturation, determine the allowed range for $R_D$ values.

d)

We want to increase the voltage gain of the amplifier. Does the gain get higher from putting a capacitor parallel to $R_S$? What about putting an inductor in series with $R_S$? What about putting an inductor in series with $R_D$?
Note: this question is related to chapters 4 and 5.