Exercise 8.7 A MOS output stage

In the output stage below, the MOS transistors are identical except for the polarity of their voltages and currents. For the NMOS transistor, $K=1\frac{A}{V^2}$ and $V_T=3V$. For the PMOS transistor these values are the same but negative. In the circuit $V_{\mathit{DD}}=15V$ and $R_L=5\mathrm{\Omega }$.

The bias current through the chain of resistors $R_1$–$R_2$–$R_2$–$R_1$ is such that for $v_G=0$ the voltage across both $R_1$-s is exactly equal to the threshold voltage $V_T$ of the transistors. The value of $R_2$ is $4.5k\mathrm{\Omega }$.

a)

Derive an expression for $R_1$ and calculate the numerical value of this resistor.

b)

Derive an equation for the input voltage $v_G$ for which the voltage at the gate of $M_1$ is equal to a value $v_X$. Also calculate the numerical value for $v_X=10V$.

c)

Verify that for the situation in b) the transistor $M_2$ is off.

d)

Calculate the drain current of $M_1$ and the output voltage $v_{\mathit{OUT}}$.

e)

Calculate the output voltage $v_{\mathit{OUT}}$ for $v_G=10V$.

f)

Calculate the output voltage $v_{\mathit{OUT}}$ at $V_G=15V$. For simplicity reasons you may assume the square law behavior for both transistors.